Abstract: Relay circuitry for a power-over-network device is provided. The relay circuitry allows power-supplying network devices to identify and subsequently to supply power across a network connection to the power-over-network device, thereby eliminating the need for external power sources. The relay circuitry is operative using only the signals transmitted along a data line across the network connection. The relay circuitry is integrated together with switching circuitry on-chip on the power-over-network device. The relay circuitry and switching circuitry are further designed to propagate both the test signals and the subsequent data signals prior to and after the turning on of the power-over-network device, respectively, with minimal signal degradation.

Abstract: A transmit canceller comprises an amplifier having a first polarity input terminal, a second polarity input terminal, and an output terminal. A feedback element communicates with the second polarity input terminal and the output terminal. A first input resistor communicates with the second polarity input terminal and a composite signal that is based on a near end transmission signal and a received signal from a far end. A second input resistor communicates with the second polarity input terminal and a replica transmitter signal. A voltage source communicates with the first polarity input terminal. The received signal is output by the output terminal.

Abstract: An electrical circuit in a communications channel is provided. The electrical circuit includes an active resistive summer. The active resistive summer has a composite signal as an input. The composite signal includes a transmission signal component and a receive signal component. A replica transmission signal is also an input to the active resistive summer. The active resistive summer includes the receive signal component as an output.

Abstract: A mixed-mode signal processor architecture provides decision feedback equalization for a communications channel. A decision circuit compares an analog signal to a predetermined threshold and outputs a digital signal based on the comparison. A mixed-mode decision feedback equalizer (DFE) includes a plurality of tap weights and produces a DFE signal using the analog signal, the digital signal, and the tap weights. A first summer has a first input that communicates with an input of the decision circuit, a second input that communicates with an output of the decision circuit, and an output. An adaptation circuit communicates with the output of the first summer and adjusts the tap weights of the mixed-mode DFE, the clock signal a timing of the clock signal of a PLL, and an automatic gain control signal of an amplifier.

Abstract: A communication circuit for an Ethernet or other network transceiver includes a first sub-circuit having a first input which receives a composite differential signal including first and second differential signal components, a second input which receives a differential replica transmission signal, and an output which provides a differential receive signal which comprises the composite differential signal minus the differential replica transmission signal. The communication circuit also includes a second sub-circuit which produces first and second single-ended replica transmission signals which together substantially comprise a replica of the first differential signal component of the composite differential signal and a third sub-circuit, which is coupled to the first and second sub-circuits, and which produces the differential replica transmission signal from the first and second single-ended replica transmission signals.

Abstract: A switching physical layer (PHY) device comprises a first termination network, a switching transmitter, and a switching receiver. The first termination network communicates with a first network connector. The switching transmitter includes first and second outputs, which communicate with the first termination network and a second termination network, respectively. The switching transmitter selectively outputs a transmit signal to a selected one of the first and second termination networks based on a control signal. The switching receiver includes first and second inputs, which communicate with the first and second termination networks, respectively. The switching receiver receives a receive signal from the selected one of the first and second termination networks.

Abstract: A circuit includes a chopper switch to receive an analog input signal and output a first chopped signal of a first polarity during a first clock phase and a second chopped signal of a second polarity during a second clock phase. An analog block receives and processes the first and second chopped signals and outputs first and second processed signals, respectively. The analog bock has a first offset voltage associated thereto. The first and second processed signals, each includes a first offset component that is associated with the first offset voltage. A data converter receives and converts the first and second processed signals into first and second digital codes, respectively. An offset canceller receives the first and second digital codes. The offset canceller is configured to remove the first offset components from the first and second digital codes and output a digital output signal corresponding to the analog input signal.

Abstract: A transmit canceller comprises an operational amplifier having a first polarity input terminal, a second polarity input terminal, and an output terminal. A feedback element communicates with the second polarity input terminal and the output terminal. A first input resistor communicates with the second polarity input terminal and the measured signal input. A second input resistor communicates with the second polarity input terminal and the replica signal input. A predetermined voltage source communicates with the first polarity input terminal of the operational amplifier. The received signal is an output at the output terminal of the operational amplifier.

Abstract: An Ethernet controller includes a decoder, and T sets of transmit circuits. Each set of transmit circuits receives one of T decoded signals from the decoder, and includes a digital-to-analog converter (DAC) that provides a transmit output signal, and a replica circuit that provides a replica output signal. Each DAC includes N current sources arranged in parallel and differentially, and M delay elements. Each current source includes a control input. A sum of outputs of the N current sources forms each transmit output signal. An input of the first delay element and the control input of the first current source receive a decoded signal. An input of an mth delay element is in communication with an output of an m?1th delay element. The output of each delay element controls a corresponding control input of a current source. A sum of the transmit output signals forms an accumulated output signal.

Abstract: A communication device includes a first polarity driver circuit. The first polarity driver circuit includes a first current source. The first polarity driver circuit includes a first amplifier. The first amplifier is arranged in a feedback configuration with the first current source. The first amplifier is configured to receive an input signal. The first polarity driver circuit includes a first cascode device. The first cascode device is arranged in a cascode configuration with the first current source. The first polarity driver circuit includes a second amplifier. The second amplifier is arranged in a feedback configuration with the first cascode device. The second amplifier is configured to receive a bias control signal.

Abstract: An Ethernet controller includes a plurality of sets of digital-to-analog converters (DACs). Each DAC receives an input signal and provides an output signal. Each of the plurality of sets of DACs includes a plurality of sets of replica current circuits. Each DAC includes current sources. Each current source includes a respective control input. The output signal provided by each DAC includes a sum of outputs of the current sources. Each DAC also includes delay elements. An input of a first one of the delay elements receives the input signal. An mth one of the delay elements includes an input in communication with an m-1th one of the delay elements. An output of one of the delay elements controls a corresponding control input of one of the current sources. A sum of each output signal from a respective one of the plurality of sets of DACs forms an accumulated output signal.

Abstract: A self-repairable semiconductor comprises a first device and a replacement device. A switching device selectively swaps the replacement device for the first device when the first device is non-operable. The switching device includes an analog switching circuit that selects one of a first pair of differential outputs of the first device having a first common mode voltage and a second pair of differential outputs of the replacement device having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches.

Abstract: An analog-to-digital converter having N comparators is provided. Each one of the N comparators receives a common analog input signal at a corresponding first input, and each one of the N comparators provides an output representing one bit of an N-bit digital conversion of the common analog input signal. The analog-to-digital converter generates the N-bit digital conversion of the common analog input signal without using a reference clock.

Abstract: An Ethernet controller includes a decoder, and T sets of transmit circuits. Each set of transmit circuits receives one of T decoded signals from the decoder, and includes a digital-to-analog converter (DAC) that provides a transmit output signal, and a replica circuit that provides a replica output signal. Each DAC includes N current sources arranged in parallel and differentially, and M delay elements. Each current source includes a control input. A sum of outputs of the N current sources forms each transmit output signal. An input of the first delay element and the control input of the first current source receive a decoded signal. An input of an mth delay element is in communication with an output of an m?1th delay element. The output of each delay element controls a corresponding control input of a current source. A sum of the transmit output signals forms an accumulated output signal.

Abstract: An Ethernet controller includes a decoder, and T sets of transmit circuits. Each set of transmit circuits receives one of T decoded signals from the decoder, and includes a digital-to-analog converter (DAC) that provides a transmit output signal, and a replica circuit that provides a replica output signal. Each DAC includes N current sources arranged in parallel and differentially, and M delay elements. Each current source includes a control input. A sum of outputs of the N current sources forms each transmit output signal. An input of the first delay element and the control input of the first current source receive a decoded signal. An input of an mth delay element is in communication with an output of an m?1th delay element. The output of each delay element controls a corresponding control input of a current source. A sum of the transmit output signals forms an accumulated output signal.

Abstract: Systems, methods and apparatus relating to electronic circuits and signal processing are provided. In one aspect, a circuit is provided that includes a charge-pump operable to supply an output voltage, and a current mirror in communication with the charge-pump. The current mirror is responsive to the output voltage of the charge pump, and is operable to output a relatively constant current and suppress noise from the output voltage.

Abstract: An analog switching circuit selects one of a first pair of differential outputs of a first circuit having a first common mode voltage and a second pair of differential outputs of a second circuit having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An operational amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches. A common mode feedback circuit communicates with the first and second inputs of the operational amplifier and maintains a common mode voltage input of the amplifier below the first and second common mode voltages.

Abstract: A nonlinearity detection system for an analog to digital converter (ADC) comprises a signal generator that generates a periodic signal that is output to the ADC and that comprises first and second intervals. The periodic signal monotonically increases during the first interval and monotonically decreases during the second interval. A differentiator module communicates with the ADC and that generates an output signal that is based on an output of the ADC and a delayed output of the ADC. A nonlinearity detection module detects slope discontinuities in the output signal of the differentiator module.

Abstract: A nonlinearity detection system and method for an analog to digital converter (ADC) includes a triangular wave generator that generates a triangular wave that is output to the ADC. A differentiator module communicates with the ADC and generates an output signal that is based on an output of the ADC and a delayed output of the ADC. A nonlinearity detection module detects slope discontinuities in the output signal of the differentiator module.

Abstract: An analog switching circuit selects one of a first pair of differential outputs of a first circuit having a first common mode voltage and a second pair of differential outputs of a second circuit having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An operational amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches. A common mode feedback circuit communicates with the first and second inputs of the operational amplifier and maintains a common mode voltage input of the amplifier below the first and second common mode voltages.