Abstract: Circuits and methods for compensating for an input-dependent gain error in a buffer and/or amplifier circuit, including applying a dynamic current to the input transistor. Circuits generally include a dynamic current supply coupled to a terminal of the input transistor, the dynamic current supply providing a compensating current. The compensating current can have a magnitude equal to the output impedance of the input transistor times a magnitude of the output voltage. The compensating current can be provided via a current mirror, or directly to a terminal of the input transistor. Methods generally include regulating variations in the current through the input transistor by sinking or sourcing a static current and a dynamic current at a terminal of the input transistor. The dynamic current can be regulated in response to a variation in the input signal.

Abstract: A circuit configured to generate an analog signal having a pre-determined pattern. The circuit includes a plurality of digital-to-analog converters. Each of the plurality of digital-to-analog converters includes a plurality of current sources configured to generate a plurality of square waveforms and a summer configured to sum the plurality of square waveforms to generate the analog signal having the pre-determined pattern. Each square waveform is delayed by a pre-determined amount delay relative to another square waveform of the plurality of square waveforms. The pre-determined amount of delay between each square waveform of the plurality of waveforms is adjustable to adjust the pre-determined pattern of the analog signal. The pre-determined amount of delay is non-uniform throughout the circuit.

Abstract: In one embodiment, a first resistor ladder includes a first voltage across the first resistor ladder. A second resistor ladder includes a second voltage across the second resistor ladder. A third resistor ladder includes a third voltage across the third resistor ladder. The calibrator receives the first voltage and third voltage and adjusts a current through the third resistor ladder to adjust the third voltage based on the received first voltage and third voltage. A buffer is configured to provide buffering for the third resistor ladder from the second resistor ladder. The third voltage of the third resistor ladder is stable even though the second voltage of the second resistor ladder is changing.

Abstract: In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to the capacitance. This prevents the asynchronous sampling that occurs in a zero-crossing position in the incoming data from remaining in that position in subsequent sampling cycles, so that a valid signal is not missed by the detector.

Abstract: In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.

Abstract: Relay circuitry for a power-over-network device is provided. The relay circuitry allows power-supplying network devices to identify and subsequently to supply power across a network connection to the power-over-network device, thereby eliminating the need for external power sources. The relay circuitry is operative using only the signals transmitted along a data line across the network connection. The relay circuitry is integrated together with switching circuitry on-chip on the power-over-network device. The relay circuitry and switching circuitry are further designed to propagate both the test signals and the subsequent data signals prior to and after the turning on of the power-over-network device, respectively, with minimal signal degradation.

Abstract: A system for reducing electromagnetic interference and ground bounce in an information communication system includes a plurality of information communication devices. Each of the plurality of information communication devices is responsive to a respective information communication clock signal. Each information communication clock signal of each of the plurality of information communication devices is associated with a common reference clock signal. The system includes a phase controller. The phase controller is responsive to the common reference clock signal. The phase controller alters a phase of each information communication clock signal of each of the plurality of information communication devices by a predetermined amount.

Abstract: A switching physical layer (PHY) device comprises a first termination network, a switching transmitter, and a switching receiver. The first termination network communicates with a first network connector. The switching transmitter includes first and second outputs, which communicate with the first termination network and a second termination network, respectively. The switching transmitter selectively outputs a transmit signal to a selected one of the first and second termination networks based on a control signal. The switching receiver includes first and second inputs, which communicate with the first and second termination networks, respectively. The switching receiver receives a receive signal from the selected one of the first and second termination networks.

Abstract: A system and method for transmitting information includes a first driver circuit configured to generate a first component signal of a differential signal at a first polarity. The system includes a second driver circuit configured to generate a second component signal of the differential signal at a second polarity. The first and second component signals are biased to form biased first and second component signals. A differential amplitude of a combination of the biased first and second component signals is less than a corresponding differential amplitude of the differential signal. The system includes an offset signal circuit in communication with the first and second driver circuits. The offset signal circuit is configured to generate an offset signal for offsetting the biased first and second component signals. A combination of the offset and biased first and second component signals forms the differential signal.

Abstract: In one embodiment, a first resistor ladder includes a first voltage across the first resistor ladder. A second resistor ladder includes a second voltage across the second resistor ladder. A third resistor ladder includes a third voltage across the third resistor ladder. The calibrator receives the first voltage and third voltage and adjusts a current through the third resistor ladder to adjust the third voltage based on the received first voltage and third voltage. A buffer is configured to provide buffering for the third resistor ladder from the second resistor ladder. The third voltage of the third resistor ladder is stable even though the second voltage of the second resistor ladder is changing.

Abstract: First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. In one embodiment, the coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. A switch matrix includes a plurality of switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides a plurality of fine references. A fine ADC performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.

Abstract: A communication circuit includes a replica circuit that generates first and second single-ended replica transmit signals. When one of the first and second single-ended replica transmit signals is asserted, the other of the first and second single-ended replica transmit signals is not asserted. A converter circuit includes a differential amplifier including first and second inputs that receive the first and second single-ended replica transmit signals, respectively. The converter circuit converts the first and second single-ended replica transmit signals to a differential replica transmit signal. A receive circuit generates a differential receive signal based on a differential composite signal and the differential replica transmit signal.

Abstract: A communication device includes a first polarity driver circuit including a first current source, a first amplifier that receives an input signal, that controls the first current source, and that receives a signal from the first current source, a first cascode device arranged in a cascode configuration with the first current source, and a second amplifier that receives a bias signal, that controls the first cascode device, and that receives a signal from the first cascode device.

Abstract: A circuit includes T sets of digital to analog converters (DACs), each including N current sources and M delay elements. An output signal includes a sum of outputs of the N current sources. An input of a first one of the M delay elements and a control input of a first one of the N current sources receive a respective one of a plurality of decoded signals. T sets of first converters each have a feedback node, an output, and an input that communicates with the output signal of a respective one of the T sets of DACs. T second converters have inputs that communicate with respective ones of the feedback nodes of each of the T sets of first converters. A summer generates a difference signal that is based on the outputs of the T sets of first converters and outputs of the T second converters.

Abstract: A system includes a transceiver configured to receive a composite signal. The composite signal is a composite of a transmit signal and a receive signal. A replica transmitter is configured to generate a replica transmit signal based on the transmit signal. A transmit canceller is configured to recover the receive signal at least in part by resistively summing the composite signal and the replica transmit signal.

Abstract: A circuit includes T sets of digital to analog converters (DACs), each including N current sources and M delay elements. An output signal includes a sum of outputs of the N current sources. An input of a first one of the M delay elements and a control input of a first one of the N current sources receive a respective one of a plurality of decoded signals. T sets of first converters each have a feedback node, an output, and an input that communicates with the output signal of a respective one of the T sets of DACs. T second converters have inputs that communicate with respective ones of the feedback nodes of each of the T sets of first converters. A summer generates a difference signal that is based on the outputs of the T sets of first converters and outputs of the T second converters.

Abstract: In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to the capacitance. This prevents the asynchronous sampling that occurs in a zero-crossing position in the incoming data from remaining in that position in subsequent sampling cycles, so that a valid signal is not missed by the detector.

Abstract: An electrical circuit in a communications channel includes a first sub-circuit having a first input which receives a composite signal that includes a transmission signal component and a receive signal component, a second input which receives a replica transmission signal, a third input which receives an analog baseline correction current, and an output which provides a receive signal which comprises the composite signal minus the replica signal. A second sub-circuit for controls the analog baseline correction current, so that the magnitude of the composite signal does not exceed a predetermined value of an operating parameter of the electrical circuit. The composite signal, the replica transmission signal, and the analog baseline correction current are directly connected together at a common node of the first sub-circuit.

Abstract: A mixed-mode signal processor includes a first summer having a first input that receives a first analog signal, a second input and an output that supplies a second analog signal. A decision circuit outputs a digital signal based on the second analog signal. A mixed-mode decision feedback equalizer (DFE) includes a plurality of tap weights and outputs a DFE signal to the second input of the summer based on the first analog signal, the digital signal and the plurality of tap weights.

Abstract: A communication circuit, Ethernet controller card, and method comprises K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding analog control signal, wherein K is at least two; K voltage-to-current converters each providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and wherein the corresponding bi-level transmit signal components of each of the K voltage-to-current converters are combined to produce a J-level transmit signal, wherein J=K+1.