Abstract: An analog amplitude pre-distortion circuit and method. The circuit includes an RF input for receiving an RF signal. The circuit also includes an amplifier stage comprising an amplifier stage input coupled to the RF input, wherein the amplifier stage is operable to amplify the RF signal to produce an amplified RF signal. The circuit further includes a bias circuit. The bias circuit includes a transistor having a first current terminal, a second current terminal and a control terminal, wherein the first current terminal is coupled to the amplifier stage input and wherein the second current terminal is coupled to a reference potential. The bias circuit also includes a resistor coupled between the amplifier stage input and the control terminal. The bias circuit also includes a variable reactance component coupled to the control terminal. The bias circuit further includes a capacitor coupled between the control terminal and the reference potential.

Abstract: An analog amplitude pre-distortion circuit and method. The circuit includes a Radio Frequency, RF, input for receiving an RF signal. The circuit also includes an amplifier stage comprising an amplifier stage input for receiving the RF signal from the RF input, wherein the amplifier stage is operable to amplify the RF signal to produce an amplified RF signal. The circuit further includes a bias circuit. The bias circuit includes a detector stage for detecting an amplitude of the RF signal, and for producing a correction signal based on the amplitude of the RF signal. The bias circuit also includes a bias application stage coupled to the amplifier stage input.

Abstract: A Wilkinson power combiner (202) is described that includes: at least one input port (210) coupled to at least one output port (212, 214, 216, 218) by at least two power combining stages. A first power combining stage (204) of the at least two power combining stages is configured as a single-stage first frequency pass circuit and a second power combining stage (206) of the at least two stages is configured as a single-stage second frequency pass circuit, and wherein the first frequency is different to the second frequency.

Abstract: A Wilkinson power combiner (202) is described that includes a high-pass, HP, frequency circuit (500, 550), wherein the HP frequency circuit (500, 550) comprises at least one of: (i) one input port (510) coupled to at least two output ports (512, 514) via at least two paths; and an input shunt inductor (520) coupling the input port (510) to ground; wherein the one input port (510) is coupled to the at least two output ports (512, 514) via respective series capacitances (230, 238) on the at least two paths, which in cooperation with the input shunt inductor (520) forms a first HP frequency circuit; and (ii) at least one resistor (554, 528)-inductor (552, 524), R-L isolation circuit (500, 550) configured to couple the at least two output ports (512, 514) that forms a second HP frequency circuit.

Abstract: A multiple-stage splitter/combiner circuit includes first and second splitter/combiner circuits coupled together. The first splitter/combiner circuit has first, second, and third input/output (I/O) ports, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with first and second terminals coupled to the second and third I/O ports, respectively. The second splitter/combiner circuit has fourth, fifth, and sixth I/O ports, and a ring of multiple quarter wave lines, which includes third and fourth quarter wave lines. The third and fourth quarter wave lines each extend from the fourth I/O port in different directions from each other to the fifth and sixth I/O ports, respectively.

Abstract: An apparatus comprising: a cascode arrangement comprising two or more transistors, the cascode arrangement coupled between a supply voltage terminal for receiving a supply voltage from a battery and a ground terminal, and a bias voltage generator configured to provide a bias voltage to at least one of the two or more transistors of the cascode arrangement to bias the cascode arrangement, the bias voltage generator further configured to increase the bias voltage with increasing supply voltage at a first rate over a first supply voltage range and increase the bias voltage with increasing supply voltage at a second rate, greater than the first rate, over a second supply voltage range, wherein the second supply voltage range comprises a range of voltages greater than the first supply voltage range.

Abstract: An inductor and a method of making an inductor. The inductor includes a stack of dielectric layers. The inductor also includes a plurality of metal levels comprising patterned metallic features of the inductor. Each metal level is located at an interface between adjacent dielectric layers in the stack. The patterned metallic features include a first plurality of inductor windings arranged in a substantially flat spiral in one of the metal levels. The patterned metallic features also include a second plurality of inductor windings in which each winding is located in a respective one of the plurality of metal levels. The first plurality of windings is connected in series with the second plurality of windings.

Abstract: A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

Abstract: A radio frequency, RF, switch circuit (201, 301, 401, 501, 601, 701, 751, 801) includes at least one first PiN diode device (252, 352, 452, 552, 652, 752, 852, 945) configured to sink or source a first alternating current; and an impedance inversion circuit (222, 322, 422, 522, 622, 722, 822, 922), connected to the at least one first PiN diode device and arranged to provide a transformed impedance between a first side of the impedance inversion circuit and a second side of the impedance inversion circuit. The RF switch further includes a second diode-based device (254, 354, 454, 554, 654, 754, 854, 945) configured to source or sink a second alternating current; and a bias circuit (330, 430, 530, 630, 830, 930) connected to at least one of the at least one first PiN diode device and the second diode-based device, wherein the at least one first PiN diode device cooperates with the second diode-based device as a push-pull current circuit.

Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.

Abstract: A radio frequency, RF, auto-transformer circuit (300, 700, 901) and method (1000) of constructing a RF auto-transformer are described. The RF, auto-transformer circuit (300, 700, 901) includes: an inner coil formed (1102) with a first metal layer (MT1) to create a first shunt inductor (302), wherein at least a portion of the inner coil is overlayed (1106) with a second metal layer (MT2) that creates a first series inductor (303) that exhibits inductive coupling to the first shunt inductor (302). An outer coil is formed (1104) with the first metal layer (MT1) that creates a second series inductor (304), where the outer coil is located adjacent the inner coil and provides inductive coupling between the second series inductor (304) and each of the first shunt inductor (302) and first series inductor (303).

Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias.

Abstract: A Wilkinson power combiner (202) is described that includes a high-pass, HP, frequency circuit (500, 550), wherein the HP frequency circuit (500, 550) comprises at least one of: (i) one input port (510) coupled to at least two output ports (512, 514) via at least two paths; and an input shunt inductor (520) coupling the input port (510) to ground; wherein the one input port (510) is coupled to the at least two output ports (512, 514) via respective series capacitances (230, 238) on the at least two paths, which in cooperation with the input shunt inductor (520) forms a first HP frequency circuit; and (ii) at least one resistor (554, 528)-inductor (552, 524), R-L isolation circuit (500, 550) configured to couple the at least two output ports (512, 514) that forms a second HP frequency circuit.

Abstract: A radio frequency, RF, switch circuit (201, 301, 401, 501, 601, 701, 751, 801) includes at least one first PiN diode device (252, 352, 452, 552, 652, 752, 852, 945) configured to sink or source a first alternating current; and an impedance inversion circuit (222, 322, 422, 522, 622, 722, 822, 922), connected to the at least one first PiN diode device and arranged to provide a transformed impedance between a first side of the impedance inversion circuit and a second side of the impedance inversion circuit. The RF switch further includes a second diode-based device (254, 354, 454, 554, 654, 754, 854, 945) configured to source or sink a second alternating current; and a bias circuit (330, 430, 530, 630, 830, 930) connected to at least one of the at least one first PiN diode device and the second diode-based device, wherein the at least one first PiN diode device cooperates with the second diode-based device as a push-pull current circuit.

Abstract: A Wilkinson power combiner (202) is described that includes: at least one input port (210) coupled to at least one output port (212, 214, 216, 218) by at least two power combining stages. A first power combining stage (204) of the at least two power combining stages is configured as a single-stage first frequency pass circuit and a second power combining stage (206) of the at least two stages is configured as a single-stage second frequency pass circuit, and wherein the first frequency is different to the second frequency.

Abstract: The present invention relates to a method for treating synthesis gas, from an indirect or direct gasifier; the method including steps for: allowing the gas within a predetermined entry temperature range to flow into a first heat exchanger, allowing the gas to flow through the first heat exchanger while exchanging heat to a first medium, allowing the gas to transfer from the first heat exchanger to a subsequent last heat exchanger, allowing the gas to flow though the last heat exchanger while exchanging heat to a last medium, and allowing the gas to exit the last heat exchanger for being available to a further treatment, such as a cleaning treatment, within a predetermined exit temperature range, preferably below an ash or mineral solidification point. Furthermore, the present invention relates to a cooling system for cooling of synthesis gas and to a gasification system.

Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.

Abstract: A switch arrangement comprising: a transceiver node coupled to a first and second circuit branch, the first circuit branch including a transmit node, the second circuit branch including a receive node; wherein the first circuit branch comprises an inductor coupled in series and a first semiconductor switch, in parallel, configured to provide a switched coupling to a reference voltage; and wherein the second circuit branch comprises one of: i) a second and third semiconductor switch; and ii) a second semiconductor switch and a third semiconductor switch configured to control the application of a supply voltage to an amplifier; and iii) a further semiconductor switch configured to control the application of a bias current to an amplifier; wherein in the first switch mode, impedance matching between the transceiver node and transmit node is provided; in the second switch mode, impedance matching between the transceiver node and receive node is provided.

Abstract: A power amplifier. The power amplifier includes a plurality of parallel coupled transistors. Each transistor has a control terminal coupled to receive a signal to be amplified and an output terminal coupled to a node. The power amplifier also includes a matching network having an input coupled to the node and an output coupleable to a load. The power amplifier further includes a first circuit branch forming a choke and harmonic trap of the power amplifier. The first circuit branch includes a first inductance, a second inductance and a first capacitor. The first inductance has a first terminal coupled to the node and a second terminal coupled to a first terminal of the second inductance. A second terminal of the second inductance is coupled to AC ground. The first capacitor is coupled in parallel with the second inductance.

Abstract: A switch arrangement comprising: a transceiver node coupled to a first and second circuit branch, the first circuit branch including a transmit node, the second circuit branch including a receive node; wherein the first circuit branch comprises an inductor coupled in series and a first semiconductor switch, in parallel, configured to provide a switched coupling to a reference voltage; and wherein the second circuit branch comprises one of: i) a second and third semiconductor switch; and ii) a second semiconductor switch and a third semiconductor switch configured to control the application of a supply voltage to an amplifier; and iii) a further semiconductor switch configured to control the application of a bias current to an amplifier; wherein in the first switch mode, impedance matching between the transceiver node and transmit node is provided; in the second switch mode, impedance matching between the transceiver node and receive node is provided,