Abstract: A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier. The buffer provides additional base current to the amplifier circuit of bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.

Abstract: A power amplifier. The power amplifier includes a plurality of parallel coupled transistors. Each transistor has a control terminal coupled to receive a signal to be amplified and an output terminal coupled to a node. The power amplifier also includes a matching network having an input coupled to the node and an output coupleable to a load. The power amplifier further includes a first circuit branch forming a choke and harmonic trap of the power amplifier. The first circuit branch includes a first inductance, a second inductance and a first capacitor. The first inductance has a first terminal coupled to the node and a second terminal coupled to a first terminal of the second inductance. A second terminal of the second inductance is coupled to AC ground. The first capacitor is coupled in parallel with the second inductance.

Abstract: An inductor and a method of making an inductor. The inductor includes a stack of dielectric layers. The inductor also includes a plurality of metal levels comprising patterned metallic features of the inductor. Each metal level is located at an interface between adjacent dielectric layers in the stack. The patterned metallic features include a first plurality of inductor windings arranged in a substantially flat spiral in one of the metal levels. The patterned metallic features also include a second plurality of inductor windings in which each winding is located in a respective one of the plurality of metal levels. The first plurality of windings is connected in series with the second plurality of windings.

Abstract: A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier. The buffer provides additional base current to the amplifier circuit of bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.

Abstract: An RF amplifier is described including an input, an output, a parallel arrangement of a first branch and at least one further branch, each branch comprising a bipolar transistor in a degenerative emitter configuration having a base coupled to the input, a collector coupled to a common collector node, and an emitter degeneration impedance arranged between the emitter and a common rail. The common collector node is coupled to the output, the base of the first branch bipolar transistor is biased at a first bias voltage and the base of the at least one further branch bipolar transistor is biased at a bias voltage offset from the first bias voltage. In operation of the RF amplifier a IM3 distortion current output by the first branch bipolar transistor is in antiphase to a IM3 distortion current output by the at least one further branch bipolar transistor.

Abstract: A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.

Abstract: A Doherty amplifier comprising: a main-power-amplifier having a main-amp-output-terminal; a peaking-power-amplifier having a peaking-amp-output-terminal; a combining node; a main-output-impedance-inverter connected between the main-amp-output-terminal and the combining node; and a transformer connected between the peaking-amp-output-terminal and the combining node.

Abstract: A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.

Abstract: An RF amplifier is described including an input, an output, a parallel arrangement of a first branch and at least one further branch, each branch comprising a bipolar transistor in a degenerative emitter configuration having a base coupled to the input, a collector coupled to a common collector node, and an emitter degeneration impedance arranged between the emitter and a common rail. The common collector node is coupled to the output, the base of the first branch bipolar transistor is biased at a first bias voltage and the base of the at least one further branch bipolar transistor is biased at a bias voltage offset from the first bias voltage. In operation of the RF amplifier a IM3 distortion current output by the first branch bipolar transistor is in antiphase to a IM3 distortion current output by the at least one further branch bipolar transistor.

Abstract: The present invention relates to a method for treating synthesis gas, from an indirect or direct gasifier; the method including steps for: allowing the gas within a predetermined entry temperature range to flow into a first heat exchanger, allowing the gas to flow through the first heat exchanger while exchanging heat to a first medium, allowing the gas to transfer from the first heat exchanger to a subsequent last heat exchanger, allowing the gas to flow though the last heat exchanger while exchanging heat to a last medium, and allowing the gas to exit the last heat exchanger for being available to a further treatment, such as a cleaning treatment, within a predetermined exit temperature range, preferably below an ash or mineral solidification point. Furthermore, the present invention relates to a cooling system for cooling of synthesis gas and to a gasification system.

Abstract: A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.

Abstract: A Doherty amplifier comprising: a main-power-amplifier having a main-amp-output-terminal; a peaking-power-amplifier having a peaking-amp-output-terminal; a combining node; a main-output-impedance-inverter connected between the main-amp-output-terminal and the combining node; and a transformer connected between the peaking-amp-output-terminal and the combining node.

Abstract: A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.

Abstract: Lumped-element based class-E Chireix combiners are disclosed that are equivalents of a quarter-wave transmission line combiner. The proposed class-E equivalent power amplifier circuits that are used can be derived from a parallel tuned class-E implementation. The proposed low-pass equivalents can behave similarly in terms of class-E performance, but absorb the 90 degree transmission line.

Abstract: The invention provides a transmitter comprising two (or more) phase locked loops controlling respective oscillators, and implementing different phase modulation. Multiple phases are derived from the respective oscillators, and an edge rotator forms an output signal from a combination of the phases. The oscillators can operate at different frequencies, neither of which is an integer multiple of the other, whereas the output signals of the multiplexers of the first and second phase locked loops are closer in frequency and can be the same. This reduces the problem of pulling, with a circuit that can be implemented with low power and area and with the versatility of being digitally intensive.

Abstract: An amplifier circuit comprising a driver (204, 304) configured to provide a switched mode input signal, a switching mode power amplifier (206, 306) configured to receive the switched mode input signal and provide an output signal for an external load (210, 310); and a sensor (208, 308) configured to sense the impedance of the external load (210, 310) The driver is configured to set the duty cycle of the switched mode input signal in accordance with the sensed impedance of the external load (210, 310).

Abstract: A bond wire transformer comprises a plurality of primary bond wires coupled in parallel; and a plurality of secondary bond wires coupled in parallel, each secondary bond wire being spaced apart from and oriented relative to a corresponding primary bond wire so as to achieve a desired mutual inductance between the corresponding primary and secondary bond wires, thereby providing magnetic coupling between the primary and secondary bond wires.

Abstract: Lumped-element based class-E Chireix combiners are disclosed that are equivalents of a quarter-wave transmission line combiner. The proposed class-E equivalent power amplifier circuits that are used can be derived from a parallel tuned class-E implementation. The proposed low-pass equivalents can behave similarly in terms of class-E performance, but absorb the 90 degree to transmission line.

Abstract: A power amplifier circuit uses an output transistor and a cascode transistor. First and second drive circuits apply gate control signals to the two transistors, which rise and fall in synchronism, and this is such that the voltage drop across the cascode transistor is reduced (compared to a constant gate voltage being applied to the output transistor).

Abstract: An amplifier circuit comprising a driver (204, 304) configured to provide a switched mode input signal, a switching mode power amplifier (206, 306) configured to receive the switched mode input signal and provide an output signal for an external load (210, 310); and a sensor (208, 308) configured to sense the impedance of the external load (210, 310) The driver is configured to set the duty cycle of the switched mode input signal in accordance with the sensed impedance of the external load (210, 310).