Patents by Inventor Pin Su
Pin Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087861Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
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Publication number: 20240087980Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.Type: ApplicationFiled: February 17, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Yen-Pin HSU, Li-Ling SU, Ming-Hsien LIN, Hsiao-Kang CHANG
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Patent number: 11923409Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
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Publication number: 20230348673Abstract: The present disclosure provides a toughened resin composition, which includes: (A) a toughened and modified compound, which includes a styrene maleic anhydride compound, an anhydride grafted olefin polymer, and a diisocyanate compound; (B) a thermosetting polymer; and (C) a toughening resin; wherein, in the toughened and modified compound, the diisocyanate compound forms a polyimide bond with the styrene maleic anhydride compound and the anhydride grafted olefin polymer, respectively. The present disclosure has high toughness and excellent mechanical properties; thus, it may have a wide range of applications in the fields of electronics, aerospace and the like.Type: ApplicationFiled: October 12, 2022Publication date: November 2, 2023Inventors: Sheng-Yen WU, Po-Hsun LEE, Chun-Ming CHIU, Wen-Pin SU, Jui-Teng HSU, Chen-Yu HUANG, Chun-Han LIN
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Publication number: 20230298385Abstract: A method for fingerprint enrollment according to an embodiment includes extracting fingerprint feature points of a fingerprint image, fragmenting the fingerprint image in units of each fingerprint feature point, to obtain a feature fragment corresponding to each fingerprint feature point, and determining, according to whether the feature fragment meets an enrollment condition, whether the fingerprint enrollment is completed. Each fingerprint image can be fully utilized, so that the count of presses on the fingerprint sensor by a user of fingerprint enrollment is reduced, and the enrollment experience of the user is improved.Type: ApplicationFiled: November 30, 2022Publication date: September 21, 2023Inventors: YUAN-LIN CHIANG, YU-CHUN CHENG, CHIEH-PIN SU
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Patent number: 11631447Abstract: A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.Type: GrantFiled: July 25, 2019Date of Patent: April 18, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Wei-Xiang You, Pin Su, Kai-Shin Li, Chenming Hu
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Publication number: 20230066359Abstract: A rehabilitation assistant system for a patient with depression is provided, comprising a support unit, an audio stimulation unit, an acupoint stimulation unit, an electronic stimulation unit, a display and optical frequency-flashed stimulation and an exercise unit. The audio stimulation unit comprises two speakers configured for broadcasting a binaural beats with frequency following response which has an audio frequency difference to two ears of the user. The acupoint stimulation unit comprises acupoint agents, and at least a part of the acupoint agents are arranged on the support unit. The electronic stimulation unit comprises two electrical stimulation agents arranged on the support unit, and the display and optical frequency-flashed stimulation is arranged on the support unit and is switchable between a display mode and an optical frequency-flashed stimulation mode so that multiple stimulations are performed simultaneously in a single treatment course.Type: ApplicationFiled: August 26, 2022Publication date: March 2, 2023Inventors: Shang-Yu YANG, Shin-Da LEE, Kuan-Pin SU, Chen-Chao HSU
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Patent number: 11567274Abstract: An optical module includes a waveguide interposer and at least one light source unit. The waveguide interposer includes at least one input terminal, at least one waveguide channel, and at least one output terminal. The at least one input terminal is configured to receive laser light, and the at least one waveguide channel is coupled to the at least one input terminal and is configured to guide the laser light. Each light source unit is configured to output the laser light to a corresponding input terminal of the at least one input terminal.Type: GrantFiled: July 30, 2021Date of Patent: January 31, 2023Assignee: Molex, LLCInventors: Sung-Ping Huang, Zuon-Min Chuang, Lung-Hua Huang, Sheng-Pin Su
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Patent number: 11556654Abstract: A system is provided to perform secure operations. The system includes an I/O subsystem, a memory subsystem and processors. The processors are operative to execute processes in trusted execution environments (TEEs) and rich execution environments (REEs). Each of the TEEs and the REEs is identified by a corresponding access identifier (AID) and protected by a corresponding system resource protection unit (SRPU). The corresponding SRPU of a TEE includes instructions, when executed by a corresponding processor, cause the corresponding processor to control access to the TEE using a data structure including allowed AIDs and pointers to memory locations accessible by the allowed AIDs.Type: GrantFiled: November 24, 2020Date of Patent: January 17, 2023Assignee: MediaTek Inc.Inventors: Yu-Tien Chang, Chih-Pin Su, Hungwen Li
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Publication number: 20220366959Abstract: A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Wei-Xiang YOU, Pin SU, Kai-Shin LI, Chenming HU
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Patent number: 11473115Abstract: The invention discloses an exopolysaccharide from Rhodopseudomonas palustris and a method for preparing and use thereof, and the method for preparing comprises the steps of: 1) keeping a seed solution from Rhodopseudomonas palustris GJ-22 in a fermentation medium for fermentation culture to obtain a fermentation broth; 2) centrifuging the fermentation broth to take the supernatant, which is treated by alcohol precipitation after filtration, and then collecting the pellet from alcohol precipitation by centrifugation to obtain crude polysaccharide; 3) removing proteins from the rude polysaccharide using protease enzymolysis method and Sevag method, followed by dialysis treatment with distilled water to remove small molecules and organic solvent to obtain a polysaccharide sample; 4) purifying the polysaccharide sample through an anion exchange column and a molecular exclusion chromatography column obtain the exopolysaccharide from Rhodopseudomonas palustris.Type: GrantFiled: November 11, 2020Date of Patent: October 18, 2022Assignees: Hunan Plant Protection Institute, Changsha Agreen Bio-Tech Ltd., Co., Suzhou Ace Chemical Technology Co., Ltd.Inventors: Yong Liu, Pin Su, Zhongying Zhai, Zhuo Zhang, Haixing Yang, Jianping Dai, Bo Zhou, Deyong Zhang, Ju'e Cheng
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Publication number: 20220179677Abstract: A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.Type: ApplicationFiled: November 11, 2021Publication date: June 9, 2022Inventors: Chih-Hsiang Hsiao, Chih-Pin Su
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Publication number: 20220093071Abstract: A noise measuring device is provided. The noise measuring device includes a soundproof box, a sound receiving device, a holding device, and a driving device. The sound receiving device is disposed in the soundproof box. The holding device is disposed in the soundproof box and configured to hold a testing object. The driving device is connected with the soundproof box and configure to drive the soundproof box to rotate.Type: ApplicationFiled: August 16, 2021Publication date: March 24, 2022Inventors: Sheng-Pin SU, Yuan-I TSENG, Che-Hung LAI, Chien-Yi WANG, Chuan-Te CHANG
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Publication number: 20220050248Abstract: An optical module includes a waveguide interposer and at least one light source unit. The waveguide interposer includes at least one input terminal, at least one waveguide channel, and at least one output terminal. The at least one input terminal is configured to receive laser light, and the at least one waveguide channel is coupled to the at least one input terminal and is configured to guide the laser light. Each light source unit is configured to output the laser light to a corresponding input terminal of the at least one input terminal.Type: ApplicationFiled: July 30, 2021Publication date: February 17, 2022Applicant: Molex, LLCInventors: Sung-Ping HUANG, Zuon-Min CHUANG, Lung-Hua HUANG, Sheng-Pin SU
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Publication number: 20220042058Abstract: The invention discloses an exopolysaccharide from Rhodopseudomonas palustris and a method for preparing and use thereof, and the method for preparing comprises the steps of: 1) keeping a seed solution from Rhodopseudomonas palustris GJ-22 in a fermentation medium for fermentation culture to obtain a fermentation broth; 2) centrifuging the fermentation broth to take the supernatant, which is treated by alcohol precipitation after filtration, and then collecting the pellet from alcohol precipitation by centrifugation to obtain crude polysaccharide; 3) removing proteins from the rude polysaccharide using protease enzymolysis method and Sevag method, followed by dialysis treatment with distilled water to remove small molecules and organic solvent to obtain a polysaccharide sample; 4) purifying the polysaccharide sample through an anion exchange column and a molecular exclusion chromatography column obtain the exopolysaccharide from Rhodopseudomonas palustris.Type: ApplicationFiled: November 20, 2020Publication date: February 10, 2022Applicants: Hunan Plant Protection Institute, Changsha Agreen Bio-Tech Ltd., Co., Suzhou Ace Chemical Technology Co., Ltd.Inventors: Yong LIU, Pin SU, Zhongying ZHAI, Zhuo ZHANG, Haixing YANG, Jianping DAI, Bo ZHOU, Deyong ZHANG, Ju'e CHENG
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Patent number: 11218022Abstract: A power conversion system includes an uninterruptible power apparatus, a generator module, and a control unit. The uninterruptible power apparatus includes a conversion module and a DC-to-AC conversion unit. The control unit controls the conversion module and the generator module according a power command so that a first average power provided from a DC power source coupled to the conversion module is slowly increased or decreased, and the control unit controls the conversion module according to a bus voltage so that a second average power provided from a mains is slowly decreased or increased corresponding to the first average power.Type: GrantFiled: December 4, 2019Date of Patent: January 4, 2022Assignee: DELTA ELECTRONICS, INC.Inventors: Yuan-Fang Lai, Chiu-Feng Wang, Hao-Pin Su
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Publication number: 20210192056Abstract: A system is provided to perform secure operations. The system includes an I/O subsystem, a memory subsystem and processors. The processors are operative to execute processes in trusted execution environments (TEEs) and rich execution environments (REEs). Each of the TEEs and the REEs is identified by a corresponding access identifier (AID) and protected by a corresponding system resource protection unit (SRPU). The corresponding SRPU of a TEE includes instructions, when executed by a corresponding processor, cause the corresponding processor to control access to the TEE using a data structure including allowed AIDs and pointers to memory locations accessible by the allowed AIDs.Type: ApplicationFiled: November 24, 2020Publication date: June 24, 2021Inventors: Yu-Tien Chang, Chih-Pin Su, Hungwen Li
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Patent number: 10922737Abstract: A interactive product recommendation method is provided, including: selecting a target product from the plurality of products; loading the product information of the target product; generating a product list according to the product characteristics corresponding to the target product and the user preferences corresponding to at least one user; generating a first label list based on at least one product characteristics corresponding to the target product and the user preferences corresponding to the user, where the first label list has a plurality of first labels corresponding to different product features; and displaying the product information, the product list and the first label list in a user interface. When clicking the icon, displaying another user interface corresponding to the clicked icon. When clicking the first label, updating the product list according to the clicked first label.Type: GrantFiled: December 22, 2017Date of Patent: February 16, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Yang Guo, Yun-Cheng Chou, Chin-Sheng Yeh, Chih-Pin Su, Shin-Yi Wu
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Publication number: 20210028178Abstract: A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.Type: ApplicationFiled: July 25, 2019Publication date: January 28, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Wei-Xiang YOU, Pin SU, Kai-Shin LI, Chenming HU
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Publication number: 20200366126Abstract: A power conversion system includes an uninterruptible power apparatus, a generator module, and a control unit. The uninterruptible power apparatus includes a conversion module and a DC-to-AC conversion unit. The control unit controls the conversion module and the generator module according a power command so that a first average power provided from a DC power source coupled to the conversion module is slowly increased or decreased, and the control unit controls the conversion module according to a bus voltage so that a second average power provided from a mains is slowly decreased or increased corresponding to the first average power.Type: ApplicationFiled: December 4, 2019Publication date: November 19, 2020Inventors: Yuan-Fang LAI, Chiu-Feng WANG, Hao-Pin SU