Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

Abstract: A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Abstract: A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well.

Abstract: Methods and apparatuses pertaining to a simulated transparent device may involve capturing a first image of a surrounding of the display with a first camera, as well as capturing a second image of the user with a second camera. The methods and apparatuses may further involve constructing a see-through window of the first image, wherein, when presented on the display, the see-through window substantially matches the surrounding and creates a visual effect with which at least a portion of the display is substantially transparent to the user. The methods and apparatuses may further involve presenting the see-through window on the display. The constructing of the see-through window may involve computing a set of cropping parameters, a set of deforming parameters, or a combination of both, based on a spatial relationship among the surrounding, the display, and the user.

Abstract: A method of making a composite pixel image sensor includes forming an image sensing array; and forming a depth sensing pixel. The depth sensing pixel includes a depth sensing photodiode; a first photo storage diode; and a first transistor configured to selectively couple the depth sensing photodiode to the first photo storage diode. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the depth sensing photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node. The method includes bonding the image sensing array to the depth sensing pixel.

Abstract: A method of making a composite pixel image sensor includes forming an image sensing array; and forming a depth sensing pixel. The depth sensing pixel includes a depth sensing photodiode; a first photo storage diode; and a first transistor configured to selectively couple the depth sensing photodiode to the first photo storage diode. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the depth sensing photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node. The method includes bonding the image sensing array to the depth sensing pixel.

Abstract: The present invention provides a self-timed differential amplifier, including an amplifier unit, having a pair of read/write terminals, wherein data is read or written by a select line; a pair of precharge transistors, controlled by a control line; and a pair of cross-coupled transistors, controlled by a column select line. Moreover, a complementary differential amplifier is formed by the combination of the pair of precharge transistors and the pair of cross-coupled transistors. The pair of the precharge transistors and the pair of cross-coupled transistors are connected to the pair of read/write terminals of the amplifier unit.

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond pad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding strength between the sensor and the ASIC.

Abstract: One or more techniques or systems for bias control are provided herein. In some embodiments, the bias control relates to biasing of a column of one or more pixels for an image sensor. In some embodiments, an associated circuit includes a reset transistor, a source-follower transistor, a first transfer transistor, a first bias transistor, a second bias transistor, and a switch connected to the second bias transistor. In some embodiments, the first bias transistor and the second bias transistor bias a column of pixels at a first time. In some embodiments, the second bias transistor is turned off, thus removing a second bias at a second time. In this way, performance of the image sensor is improved, at least because the second bias transistor enables faster settling time when active, and a wide pixel operation range when switched off.

Abstract: A video processing system includes a data buffer and a storage controller. The data buffer is shared between a plurality of in-loop filters, wherein not all of the in-loop filters comply with a same video standard. The storage controller controls data access of the data buffer, wherein for each in-loop filter granted to access the data buffer, the data buffer stores a partial data of a picture processed by the in-loop filter. Another video processing system includes a storage device and a storage controller. The storage controller adaptively determines a size of a storage space according to a tile partition setting of a picture to be processed by an in-loop filter, and controls the storage device to allocate the storage space to serve as a data buffer for storing data of the in-loop filter.

Abstract: A depth sensing pixel includes a photodiode; a first photo storage device; and a first transistor configured to selectively couple the photodiode to the first photo storage device. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node.

Abstract: A method for noise simulation of a CMOS image sensor comprises performing a frequency domain noise simulation for a readout circuit of the CMOS image sensor using a computer, wherein the readout circuit includes a correlated double sampling (CDS) circuit, wherein the frequency domain noise simulation includes a CDS transfer function to refer a noise introduced by the CDS circuit back to an input node of the readout circuit. The method further comprises calculating noise at the input node of the readout circuit based on the referred back noises caused by one or more components in the readout circuit and estimating noise of the CMOS imaging sensor by comparing the calculated noise at the input node of the readout circuit to an original input signal to the readout circuit of the CMOS imaging sensor.

Abstract: A method and apparatus for loop filter processing of reconstructed video data for a video coding system are disclosed. The system receives reconstructed video data for an image unit. The loop filter processing is applied to reconstructed pixels above a deblocking boundary of the current CTU. In order to reduce line buffer requirement and/or to reduce loop filter switching for image units, the sample adaptive offset (SAO) parameter boundary and spatial-loop-filter restricted boundary for the luma and chroma components are determined by global consideration. In one embodiment, the SAO parameter boundary and the spatial-loop-filter restricted boundary are aligned for the luma and chroma components respectively. In another embodiment, the SAO parameter boundary and the spatial-loop-filter restricted boundary for the luma and chroma components are all aligned.

Abstract: In a method and apparatus for loop filter processing, a sample adaptive offset (SAO) process is applied to DF (deblocking filter)-processed pixels of current image unit according to one or more SAO parameters. Pixels within SAO parameter boundary of current image unit share the same SAO parameters. SAO parameter boundary is shifted according to a respective goal to reduce both line buffer requirement and parameter switching, where the vertical SAO parameter boundary of current image unit is shifted-left by xs lines from a vertical boundary of current image unit and the horizontal SAO parameter boundary of current image unit is shifted-up by ys lines from a horizontal boundary of current image unit. To reduce the requirement of line buffer, xs is always greater than m that corresponds to the number of pixels at each side of a horizontal edge modified by DF, ys is greater than or equal to 0.

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond bad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding between the sensor and the ASIC.

Abstract: A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. Circuitry is coupled to the pixel and is configured to determine a reset voltage of the pixel and to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the circuitry and is configured to set a voltage level of the gain selected by the circuitry.

Abstract: The present invention relates to use of osthole for manufacturing a composition for treating focal segmental glomerulosclerosis (FSGS). Particularly, the present invention discloses that osthole is effective in treating focal segmental glomerulosclerosis (FSGS), which can alleviate various symptoms and signs of FSGS, including proteinuria, renal fibrosis, glomerular epithelial hyperplasia lesion (EPHL), and macrophage/lymphocyte infiltration in the kidney, etc.

Abstract: A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.

Abstract: A method, apparatus and computer readable medium storing a corresponding computer program for decoding a video bitstream based on multiple decoder cores are disclosed. In one embodiment of the present invention, the method arranges multiple decoder cores to decode one or more frames from a video bitstream using mixed level parallel decoding. The multiple decoder cores are arranged into groups of multiple decoder cores for parallel decoding one or more frames by using one group of multiple decoder cores for said one or more frames, wherein each group of multiple decoder cores comprises one or more decoder cores. The number of frames to be decoded in the mixed level parallel decoding or which frames to be decoded in the mixed level parallel decoding is adaptively determined.

Abstract: A multi-core decoder system and an associated method use a decoding progress synchronizer to reduce bandwidth consumption for decoding a video bitstream is disclosed. In one embodiment of the present invention, the multi-core decoder system includes a shared reference data buffer coupled to the multiple decoder cores and an external memory. The shared reference data buffer stores reference data received from the external memory and provides the reference data the multiple decoder cores for decoding video data. The multi-core decoder system also includes one or more decoding progress synchronizers coupled to the multiple decoder cores to detect decoding-progress information associated with the multiple decoder cores or status information of the shared reference data buffer, and to control decoding progress for the multiple decoder cores.