Abstract: A manufacturing method of a light-emitting device is disclosed. The method provides for patterning a semiconductor stack on a first substrate in order to form multiple light-emitting mesas. A second substrate is then bonded to the multiple light-emitting mesas and a reflective structure is formed on the first substrate. A metal layer is then applied on the reflective structure and the metal layer is patterned to form multiple metal mesas corresponding to the multiple light-emitting mesas, with a portion of the reflective structure being exposed.

Abstract: An iridium-doped carbon nanotube has an atomic ratio of iridium to carbon on a surface thereof ranging from 1×10?4 to 3.5×10?4 as measured by X-ray photoelectron spectroscopy. A working electrode including the aforesaid iridium-doped carbon nanotube and a sensor including the working electrode are also disclosed in the present invention.

Abstract: An iridium-doped carbon nanotube has an atomic ratio of iridium to carbon on a surface thereof ranging from 1×10?4 to 3.5×10?4 as measured by X-ray photoelectron spectroscopy. A working electrode including the aforesaid iridium-doped carbon nanotube and a sensor including the working electrode are also disclosed in the present invention.

Abstract: A readout device comprises a readout circuit having a first switch configured to receive a pixel reset signal, a second switch configured to receive a pixel output signal, and a third switch configured to connect the first switch to the second switch. A first capacitor is connected to the first switch, a second capacitor is connected the second switch, a fourth switch is connected to the first capacitor, and a fifth switch is connected to the second capacitor. The fifth switch is connected to the fourth switch. The readout circuit also comprises a sixth switch connected to the first capacitor and a seventh switch connected to the second capacitor. The sixth switch is configured to provide a first output of the readout circuit, and the seventh is configured to provide a second output of the readout circuit.

Abstract: A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

Abstract: A manufacturing method of a light-emitting device is disclosed. The method provides for patterning a semiconductor stack on a first substrate in order to form multiple light-emitting mesas. A second substrate is then bonded to the multiple light-emitting mesas and a reflective structure is formed on the first substrate. A metal layer is then applied on the reflective structure and the metal layer is patterned to form multiple metal mesas corresponding to the multiple light-emitting mesas, with a portion of the reflective structure being exposed.

Abstract: A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state.

Abstract: A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.

Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: A method for noise simulation of a CMOS image sensor comprises performing a frequency domain noise simulation for a readout circuit of the CMOS image sensor using a computer, wherein the readout circuit includes a correlated double sampling (CDS) circuit, wherein the frequency domain noise simulation includes a CDS transfer function to refer a noise introduced by the CDS circuit back to an input node of the readout circuit. The method further comprises calculating noise at the input node of the readout circuit based on the referred back noises caused by one or more components in the readout circuit and estimating noise of the CMOS imaging sensor by comparing the calculated noise at the input node of the readout circuit to an original input signal to the readout circuit of the CMOS imaging sensor.

Abstract: Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: An apparatus comprises a readout circuit configured to be disconnected from a pixel output, and to connect a pixel reset signal received by the readout circuit to a pixel output signal received by the readout circuit. The apparatus also comprises at least one programmable gain amplifier coupled with the readout circuit. The apparatus further comprises an analog-to-digital converter coupled with the programmable gain amplifier. The readout circuit is configured to be calibrated based on a comparison of a measured output of the readout circuit to a predetermined value, the predetermined value being equal to (2n/2)?1, where n is the number of bits of the analog-to-digital converter.

Abstract: A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.

Abstract: The present invention relates to a new use of citral for manufacturing a medicament for treating focal segmental glomerulosclerosis (FSGS). Particularly, the present invention discloses that citral is effective in alleviating symptoms of FSGS, including reducing glomerular epithelial hyperplasia lesions (EPHLs), peri-glomerular inflammation or glomerular hyalinosis or sclerosis, and also reducing proteinuria or hematuria or lowering serum urea nitrogen level or serum creatinine level in the subject.

Abstract: A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.

Abstract: A light-emitting device comprises a substrate; a first semiconductor stack formed on the substrate; a connecting part formed on the first semiconductor stack; and a plurality of droplets formed near the connecting part, wherein the plurality of droplets comprises a material same as that of the connecting part.

Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.