Patents by Inventor Ping-Chia Shih

Ping-Chia Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160204230
    Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.
    Type: Application
    Filed: March 23, 2016
    Publication date: July 14, 2016
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
  • Patent number: 9330923
    Abstract: A semiconductor process includes the steps of providing a semiconductor substrate with a logic region and a memory region, defining memory gates on the memory region, forming a conformal spacer layer on the memory gates and the semiconductor substrate, and performing an etch process on the conformal spacer layer, such that the conformal spacer layer on sidewalls of the memory gates transforms into spacers, and the conformal spacer layer between the memory gates transforms into a concave block covering the semiconductor substrate between the memory gates.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ping-Chia Shih
  • Patent number: 9331183
    Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
  • Patent number: 9202701
    Abstract: A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 1, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-I Chou, Chi-Cheng Huang, Yu-Chun Chang, Ling-Hsiu Chou, Tseng-Fang Dai, Jheng-Jie Huang, Ping-Chia Shih
  • Patent number: 9129852
    Abstract: A method for fabricating a non-volatile memory semiconductor device is disclosed. The method includes the steps of providing a substrate; forming a gate pattern on the substrate, wherein the gate pattern comprises a first polysilicon layer on the substrate, an oxide-nitride-oxide (ONO) stack on the first polysilicon layer, and a second polysilicon layer on the ONO stack; forming an oxide layer on the top surface and sidewall of the gate pattern; performing a first etching process to remove part of the oxide layer; and performing a second etching process to completely remove the remaining oxide layer.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: September 8, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiang-Chen Lee, Shao-Nung Huang, Wei-Pin Huang, Kuo-Lung Li, Ling-Hsiu Chou, Ping-Chia Shih
  • Publication number: 20150179748
    Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chang, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Kun-I Chou, Chung-Che Huang, Chia-Cheng Hsu, Mu-Jia Liu
  • Patent number: 9040423
    Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: May 26, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wan-Fang Chung, Ping-Chia Shih, Hsiang-Chen Lee, Che-Hao Chang, Jhih-Long Lin, Wei-Pin Huang, Shao-Nung Huang, Yu-Cheng Wang, Jaw-Jiun Tu, Chung-Che Huang
  • Publication number: 20150024598
    Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Wan-Fang Chung, Ping-Chia Shih, Hsiang-Chen Lee, Che-Hao Chang, Jhih-Long Lin, Wei-Pin Huang, Shao-Nung Huang, Yu-Cheng Wang, Jaw-Jiun Tu, Chung-Che Huang
  • Patent number: 8921185
    Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang
  • Publication number: 20140353739
    Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
  • Publication number: 20140227844
    Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.
    Type: Application
    Filed: April 17, 2014
    Publication date: August 14, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hsiang-Chen LEE, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang
  • Patent number: 8792275
    Abstract: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: July 29, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ping-Chia Shih, Chung-Chin Shih
  • Patent number: 8742549
    Abstract: A semiconductor structure includes: a substrate with at least a trench therein, wherein the trench is filled with an insulation layer; a first polysilicon layer disposed on the insulation layer and covering at least two opposite borders of a top surface of the insulation layer; a second polysilicon layer disposed above the first polysilicon layer and the substrate; and a dielectric layer disposed between the first and second polysilicon layers, wherein the first and second polysilicon layers are respectively shaped as first and second strips.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: June 3, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Ping-Chia Shih
  • Patent number: 8722488
    Abstract: A method of fabricating a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, and a material layer covering the gate stack layers is formed on the semiconductor substrate. Subsequently, a part of the material layer is removed to form a sacrificial layer between the gate stack layers, and a spacer at the opposite lateral sides of the gate stack layers. Furthermore, a patterned mask covering the gate stack layers and the spacer and exposing the sacrificial layer is formed, and the sacrificial layer is removed.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: May 13, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Ping-Chia Shih
  • Publication number: 20140091383
    Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.
    Type: Application
    Filed: December 5, 2013
    Publication date: April 3, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Ko-Chi Chen, Ping-Chia Shih, Chih-Ming Wang, Chi-Cheng Huang, Hsiang-Chen Lee
  • Patent number: 8633079
    Abstract: A method for fabricating SONOS memory is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on the surface of the semiconductor substrate; forming a hard mask on the second silicon oxide layer; patterning the hard mask, the second silicon oxide layer, the silicon nitride layer, and the first silicon oxide layer to form a patterned hard mask and a stacked structure; forming a gate oxide layer on surface of the patterned hard mask; removing the gate oxide layer and the patterned hard mask; forming a patterned polysilicon layer on surface of the stacked structure; and forming a source/drain region in the semiconductor substrate adjacent to two sides of the polysilicon layer.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: January 21, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ping-Chia Shih, Yu-Cheng Yin
  • Patent number: 8629025
    Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: January 14, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Chi Chen, Ping-Chia Shih, Chih-Ming Wang, Chi-Cheng Huang, Hsiang-Chen Lee
  • Publication number: 20130307049
    Abstract: A method of fabricating a semiconductor device includes the following steps. At first, a semiconductor substrate is provided. A gate stack layer is formed on the semiconductor substrate, and the gate stack layer further includes a cap layer disposed thereon. Furthermore, two first spacers surrounding sidewalls of the gate stack layer is further formed. Subsequently, the cap layer is removed, and two second spacers are formed on a part of the gate stack layer. Afterwards, a part of the first spacers and the gate stack layer not overlapped with the two second spacers are removed to form two gate stack structures.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Inventor: Ping-Chia Shih
  • Patent number: 8575683
    Abstract: A method of fabricating a semiconductor device includes the following steps. At first, a semiconductor substrate is provided. A gate stack layer is formed on the semiconductor substrate, and the gate stack layer further includes a cap layer disposed thereon. Furthermore, two first spacers surrounding sidewalls of the gate stack layer is further formed. Subsequently, the cap layer is removed, and two second spacers are formed on a part of the gate stack layer. Afterwards, a part of the first spacers and the gate stack layer not overlapped with the two second spacers are removed to form two gate stack structures.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: November 5, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Ping-Chia Shih
  • Publication number: 20130280874
    Abstract: A method of fabricating a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, and a material layer covering the gate stack layers is formed on the semiconductor substrate. Subsequently, a part of the material layer is removed to form a sacrificial layer between the gate stack layers, and a spacer at the opposite lateral sides of the gate stack layers. Furthermore, a patterned mask covering the gate stack layers and the spacer and exposing the sacrificial layer is formed, and the sacrificial layer is removed.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Inventor: Ping-Chia Shih