Patents by Inventor Ping-Chia Shih

Ping-Chia Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7973353
    Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: July 5, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Sung Huang, Ping-Chia Shih, Chiao-Lin Yang, Chi-Cheng Huang
  • Publication number: 20110151672
    Abstract: An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer, the complex hard mask and the nitride layer are etched by utilizing a patterned photoresist as an etching mask, so as to expose the first oxide layer. In addition, the part of the nitride layer covering the insulating structure can be further removed. Accordingly, the present invention can effectively control layout patterns of material layers and doped regions and thereby can improve the performance of a narrow width device.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventor: Ping-Chia SHIH
  • Publication number: 20110044109
    Abstract: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.
    Type: Application
    Filed: August 18, 2009
    Publication date: February 24, 2011
    Inventors: Ping-Chia Shih, Chung-Chin Shih
  • Publication number: 20100200905
    Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 12, 2010
    Inventors: Chun-Sung Huang, Ping-Chia Shih, Chiao-Lin Yang, Chi-Cheng Huang
  • Publication number: 20090243030
    Abstract: A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Ping-Chia Shih
  • Publication number: 20090179256
    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory and the corresponding forming method are disclosed. The memory includes a plurality of select gate structures arranged in an array, a plurality of charge trap spacers that do not contact each other, and a plurality of word lines. The word lines can directly contact the select gates' surfaces of the select gate structures. All of the select gate structures disposed in one line can share two charge trap spacers, and the two charge trap spacers are disposed on the opposed sidewalls of these select gate structures.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Inventors: Sung-Bin Lin, Hwi-Huang Chen, Ping-Chia Shih
  • Patent number: 7368782
    Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: May 6, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Ping-Chia Shih, Shou-Wei Hsieh
  • Publication number: 20060199356
    Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.
    Type: Application
    Filed: January 9, 2006
    Publication date: September 7, 2006
    Inventors: Ping-Chia Shih, Shou-Wei Hsieh
  • Patent number: 7071063
    Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 4, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Ping-Chia Shih, Shou-Wei Hsieh
  • Publication number: 20060046390
    Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.
    Type: Application
    Filed: September 1, 2004
    Publication date: March 2, 2006
    Inventors: Ping-Chia Shih, Shou-Wei Hsieh