Abstract: A federated learning method includes: providing importance parameters and performance parameters by client devices respectively to a central device, performing a training procedure by the central device, wherein the training procedure includes: selecting target devices from the client devices according to a priority order associated with the importance parameters, dividing the target devices into training groups according to a similarity of the performance parameters, notifying the target devices to perform iterations according to the training groups respectively to generate trained models, transmitting the trained models to the central device, and updating a global model based on the trained models, performing the training procedure again or outputting the global model to the client devices based on a convergence value of the global model and the number of times of performing the training procedure.

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A method and a system for identifying an operating status of an electrical appliance based on non-intrusive load monitoring are provided. The method includes the following steps. Total power consumption history data of a target field and appliance power consumption history data of target electrical appliances are obtained. The appliance power consumption history data of each target electrical appliance is converted into a binary data set. The total power consumption history data is clustered into cluster samples to obtain first feature data sets, which are then dimensionally reduced into second feature data sets, and a machine learning model is trained by using the second feature data sets and the binary data sets of the target electrical appliances to establish an operation identification model for the target electrical appliances. The operation identification model identifies an operating status of the target electrical appliances according to total power consumption data.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: A test device includes a power compensation module and a test module. The power compensation module receives AC power generated by a device under test to generate DC power to the device under test. The test module provides a plurality of test signals and a test mode to the device under test for testing the device under test.

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.

Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

Abstract: A method of predicting a blood glucose level of a user, comprising: obtaining, by an image capturing device, an iris image of the user; training a first convolutional neural network of a computing device using the iris image as an input to obtain a classification of the iris image; training a second convolutional neural network of the computing device using the classification and the iris image to extract an iris feature vector; and predicting, by the computing device, the blood glucose level of the user based on the iris feature vector.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.