Patents by Inventor Ping Chiang

Ping Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180166405
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.
    Type: Application
    Filed: June 16, 2017
    Publication date: June 14, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Yung-Ping CHIANG, Nien-Fang WU, Min-Chien HSIAO, Yi-Che CHIANG, Chao-Wen SHIH, Shou-Zen CHANG, Chung-Shi LIU, Chen-Hua YU
  • Publication number: 20180096090
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.
    Type: Application
    Filed: January 20, 2017
    Publication date: April 5, 2018
    Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
  • Patent number: 9911606
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ping Chiang, Ya-Ting Chang, Wen-Li Cheng, Nian-Fuh Cheng, Ming-Hui Chih, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20170345731
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Application
    Filed: August 12, 2016
    Publication date: November 30, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20170316938
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.
    Type: Application
    Filed: September 16, 2016
    Publication date: November 2, 2017
    Inventors: Chia-Ping Chiang, Ya-Ting Chang, Wen-Li Cheng, Nian-Fuh Cheng, Ming-Hui Chih, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9728477
    Abstract: The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region. The method further includes disposing a buffer layer at least covering the scribe line, disposing a dielectric layer including an opening over each chip region, and disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region. The method further includes forming a mold over the substrate, covering the buffer layer and cutting the substrate along the scribe line. Furthermore, the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nien-Fang Wu, Chao-Wen Shih, Yung-Ping Chiang, Hao-Yi Tsai
  • Publication number: 20170113108
    Abstract: A weight-adjustable-counterbalance apparatus includes a shell and at least one or more weighting member selectively added to the shell. The shell includes a container having an annular lateral wall and an end wall, and defines an opening at an end and a compartment. A first restrainer releasably fits on the end wall and in a manner being prevented from rotating relative to the container. A second restrainer releasably fits on the end of the container and in a manner being prevented from rotating relative to the container. A fastener releasably secures the first retainer, the container, and the second retainer together. The fastener has a first end retained on the first restrainer, a body inserting into the compartment, and a second end extending outside the opening and engaging with the second restrainer. The at least one or more weighting member is added by releasably fitting on the fastener.
    Type: Application
    Filed: October 21, 2015
    Publication date: April 27, 2017
    Inventor: Kai-Ping CHIANG
  • Publication number: 20170103955
    Abstract: A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Inventors: YUNG-PING CHIANG, CHAO-WEN SHIH, HAO-YI TSAI, MIRNG-JI LII
  • Patent number: 9616307
    Abstract: A weight-adjustable-counterbalance apparatus includes a shell and at least one or more weighting member selectively added to the shell. The shell includes a container having an annular lateral wall and an end wall, and defines an opening at an end and a compartment. A first restrainer releasably fits on the end wall and in a manner being prevented from rotating relative to the container. A second restrainer releasably fits on the end of the container and in a manner being prevented from rotating relative to the container. A fastener releasably secures the first retainer, the container, and the second retainer together. The fastener has a first end retained on the first restrainer, a body inserting into the compartment, and a second end extending outside the opening and engaging with the second restrainer. The at least one or more weighting member is added by releasably fitting on the fastener.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 11, 2017
    Inventor: Kai-Ping Chiang
  • Patent number: 9543259
    Abstract: A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: January 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Hao-Yi Tsai, Mirng-Ji Lii
  • Patent number: 9484308
    Abstract: A semiconductor device includes a substrate including a pad and an alignment feature disposed over the substrate, a passivation disposed over the substrate and a periphery of the pad, a post passivation interconnect (PPI) including a via portion disposed on the pad and an elongated portion receiving a conductive bump to electrically connect the pad with the conductive bump, a polymer covering the PPI, and a molding material disposed over the polymer and around the conductive bump, wherein the molding material comprises a first portion orthogonally aligned with the alignment feature and adjacent to an edge of the semiconductor device and a second portion distal to the edge of the semiconductor device, a thickness of the first portion is substantially smaller than a thickness of the second portion, thereby the alignment feature is visible through the molding material under a predetermined radiation.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: November 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Kai Liu, Chao-Wen Shih, Yung-Ping Chiang
  • Publication number: 20160240453
    Abstract: The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region. The method further includes disposing a buffer layer at least covering the scribe line, disposing a dielectric layer including an opening over each chip region, and disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region. The method further includes forming a mold over the substrate, covering the buffer layer and cutting the substrate along the scribe line. Furthermore, the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold.
    Type: Application
    Filed: April 27, 2016
    Publication date: August 18, 2016
    Inventors: NIEN-FANG WU, CHAO-WEN SHIH, YUNG-PING CHIANG, HAO-YI TSAI
  • Patent number: 9418191
    Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chun Wang, Jeng-Horng Chen, Shy-Jay Lin, Chia-Ping Chiang, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9397056
    Abstract: In some embodiments in accordance with the present disclosure, a semiconductor device including a semiconductor substrate is received. An interconnect structure is provided over the semiconductor substrate, and a passivation is provided over the interconnect structure. The passivation includes an opening such that a portion of the interconnect structure is exposed. Moreover, a dielectric is provided over the passivation, and a post-passivation interconnect (PPI) is provided over the dielectric. The PPI is configured to connect with the exposed portion of the interconnect structure through an opening in the dielectric. Furthermore, the PPI includes a receiving area for receiving a conductor, and a trench adjacent to the receiving area. In certain embodiments, the receiving area is defined by the trench.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: July 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Ping Wang, Chao-Wen Shih, Yung-Ping Chiang, Shih-Wei Liang, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 9390223
    Abstract: A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: July 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Li Cheng, Ming-Hui Chih, Chia-Ping Chiang, Ken-Hsien Hsieh, Tsong-Hua Ou, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9390217
    Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Feng-Ju Chang, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9379076
    Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: June 28, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Chih Hsieh, Hao-Yi Tsai, Chao-Wen Shih, Yung-Ping Chiang, Tsung-Yuan Yu
  • Patent number: 9343385
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nien-Fang Wu, Chao-Wen Shih, Yung-Ping Chiang, Hao-Yi Tsai
  • Patent number: 9343415
    Abstract: In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Wen Shih, Yung-Ping Chiang, Chen-Chih Hsieh, Hao-Yi Tsai
  • Publication number: 20160099223
    Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 7, 2016
    Inventors: CHEN-CHIH HSIEH, HAO-YI TSAI, CHAO-WEN SHIH, YUNG-PING CHIANG, TSUNG-YUAN YU