Patents by Inventor Ping Chiang
Ping Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11392742Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: October 5, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 11392745Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: GrantFiled: November 30, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20220157993Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.Type: ApplicationFiled: February 4, 2022Publication date: May 19, 2022Inventors: Cheng-Ta YANG, Lu-Ping CHIANG
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Patent number: 11335666Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.Type: GrantFiled: July 9, 2020Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
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Patent number: 11289612Abstract: A flash memory device and its manufacturing method are provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.Type: GrantFiled: March 19, 2020Date of Patent: March 29, 2022Assignee: WINBOND ELECTRONICS CORP.Inventors: Cheng-Ta Yang, Lu-Ping Chiang
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Publication number: 20220013494Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
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Publication number: 20210351126Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
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Patent number: 11127708Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.Type: GrantFiled: November 7, 2019Date of Patent: September 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
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Publication number: 20210265289Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Ping CHIANG, Yi-Che CHIANG, Nien-Fang WU, Min-Chien HSIAO, Chao-Wen SHIH, Shou-Zen CHANG, Chung-Shi LIU, Chen-Hua YU
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Publication number: 20210257717Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.Type: ApplicationFiled: April 12, 2021Publication date: August 19, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
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Patent number: 11075159Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.Type: GrantFiled: July 16, 2018Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
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Patent number: 11004809Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.Type: GrantFiled: May 30, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Ping Chiang, Yi-Che Chiang, Nien-Fang Wu, Min-Chien Hsiao, Chao-Wen Shih, Shou-Zen Chang, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 10978782Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.Type: GrantFiled: April 27, 2020Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
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Publication number: 20210089697Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: ApplicationFiled: November 30, 2020Publication date: March 25, 2021Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 10937719Abstract: A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is provided. Through vias penetrating through the first molding compound are disposed around the die. The reflector pattern is disposed on the die and the through vias. The antenna structure is disposed on the reflector pattern and electrically connected with the reflector pattern and the die. The antenna structure is wrapped by a second molding compound disposed on the reflector pattern.Type: GrantFiled: June 30, 2017Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Ping Chiang, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Shou-Zen Chang, Yi-Che Chiang
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Publication number: 20210019464Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 10879170Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, a molding compound, a polymer layer, a conductive trace, a conductive via and an inductor. The semiconductor die is laterally surrounded by the molding compound. The polymer layer covers the semiconductor die and the molding compound. The conductive trace, the conductive via and the inductor are embedded in the polymer layer. The conductive via extends from a top surface of the conductive trace to a top surface of the polymer layer. The inductor has a body portion extending horizontally and a protruding portion protruded from the body portion. A total height of the body and protruding portions is substantially equal to a sum of a thickness of the conductive trace and a height of the conductive via. The height of the body portion is greater than the thickness of the conductive trace.Type: GrantFiled: April 21, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Ping Chiang, Chung-Shi Liu, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Chang-Wen Huang, Yu-Sheng Hsieh, Ching-Yu Huang
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Patent number: 10853552Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: GrantFiled: May 6, 2019Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 10847612Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.Type: GrantFiled: July 18, 2019Date of Patent: November 24, 2020Assignee: Winbond Electronics Corp.Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
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Publication number: 20200335439Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, a molding compound, a polymer layer, a conductive trace, a conductive via and an inductor. The semiconductor die is laterally surrounded by the molding compound. The polymer layer covers the semiconductor die and the molding compound. The conductive trace, the conductive via and the inductor are embedded in the polymer layer. The conductive via extends from a top surface of the conductive trace to a top surface of the polymer layer. The inductor has a body portion extending horizontally and a protruding portion protruded from the body portion. A total height of the body and protruding portions is substantially equal to a sum of a thickness of the conductive trace and a height of the conductive via. The height of the body portion is greater than the thickness of the conductive trace.Type: ApplicationFiled: April 21, 2019Publication date: October 22, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Ping Chiang, Chung-Shi Liu, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Chang-Wen Huang, Yu-Sheng Hsieh, Ching-Yu Huang