Abstract: A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

Abstract: An illuminated electronic display sign suitable for a transit vehicle comprises a support frame with a mounting surface, a plurality of lighting elements disposed on or attached to the mounting surface, and electronic circuitry configured to provide commands to selectively illuminate the lighting elements so as to create text or other information thereon. The lighting elements each comprise a semiconductor-based light source and an optical cap, each having a transparent layer portion and a diffusion layer portion. The optical caps may be generally rectangular in shape, aligned in a two-dimensional grid having rows and columns and are substantially adjacent to one another, with narrow gaps therebetween for increased display area. The optical caps may be asymmetrical, with a flat upper portion and a gradually tapering top surface to help reduce glare. A control system including wireless circuitry may be used to control multiple electronic display signs.

Abstract: In SIP network environment, a general traversal method for a port restricted NAT will become invalid when other users break in. The present invention provides four sessions for SIP, i.e. Login Session, Port Prediction Session, Multi-Traversal Session and Media Session, and the SIP network environment includes a first Internet telephone, a second Internet telephone, a symmetric NAT, a port-restricted NAT and an SIP proxy server. In the Multi-Traversal Session, the second Internet telephone sends a plurality of identical speech packets to consecutive ports of the symmetric NAT through a fixed port of the port-restricted NAT so as to achieve the NAT traversal.

Abstract: The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.

Abstract: A beverage dispensing flow control device according to one example includes a body portion, an actuation lever and a sealing gasket. A sealing gasket is securable over the bottom surface of the body and has a bottom surface with a beverage flow aperture and a vent aperture. The apertures are configured to define a maximum flow position when the sealing gasket is rotationally aligned with respect to the body portion such that the beverage flow aperture does not block the flow aperture of the body portion, and a minimum flow position when the sealing gasket is rotationally aligned with respect to the body portion such that the beverage flow aperture blocks at least the majority of the body's flow aperture while leaving at least a portion of the vent channel unblocked. A plunger is in operable communication with the actuation lever to selectively seal the bottom surface of the gasket.

Abstract: In SIP network environment, a general NAT traversal method will become invalid when an NAT with ICMP (Internet Control Message Protocol) is met. The present invention provides four sessions for SIP, i.e. Login Session, Port Prediction Session, Synchronization Session and Media Session, and the SIP network environment includes a first Internet telephone, a second Internet telephone, a first symmetric NAT, a second symmetric NAT and an SIP proxy server. The first symmetric NAT and the second symmetric NAT are ICMP-sensitive. In the Synchronization Session, the first Internet telephone and the second Internet telephone are designed to transmit packets synchronously to avoid port locking.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: A fixed-on-time controller utilizing an adaptive saw signal for discontinuous mode PFC power conversion, the fixed-on-time controller comprising: an error amplifier, having a negative input end coupled to a feedback signal, a positive input end coupled to a reference voltage, and an output end for providing a threshold signal; an adaptive current source generator, used to generate an adaptive current source according to the threshold signal; a capacitor, charged by the adaptive current source, being used for carrying a saw signal; a switch, used to discharge the capacitor under the control of a reset signal; and a comparator, having a negative input end coupled to the threshold signal, a positive input end coupled to the saw signal, and an output end for providing a turn-off signal; and a fixed-on-time driver circuit, used to provide a driving signal and the reset signal according to the turn-off signal and a sensing signal.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: The present invention provides a power saving system for smart mobile communication device in Internet communication. The power saving system comprises two smart mobile communication devices with Internet connection capability, an Internet, a server, a gateway and a mobile communication network. The two smart mobile communication devices cut off the Internet connection usually. When a smart mobile communication device performs a call through the Internet to the other smart mobile communication device, the server, the gateway and the mobile communication network are used to inform the other smart mobile communication device for Internet connection. After both sides stop the Internet communication, the two smart mobile communication devices cut off the Internet connection.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.

Abstract: A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors.