Patents by Inventor Ping-Chuan Wang

Ping-Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7710141
    Abstract: A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Giuseppe La Rosa, Kevin Kolvenbach, Ping-Chuan Wang, Stephen D. Wyatt
  • Patent number: 7701015
    Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: April 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Zhong-Xiang He, Bradley A. Orner, Vidhya Ramachandran, Alvin J. Joseph, Stephen A. St. Onge, Ping-Chuan Wang
  • Patent number: 7683651
    Abstract: A test structure for electromigration and related method are disclosed. The test structure may include an array of a plurality of multilink test sets, each multilink test set including a plurality of metal lines positioned within a dielectric material and connected in a serial configuration; each multilink test set being connected in a parallel configuration with the other multilink test sets, the parallel configuration including a first electrical connection to a cathode end of a first metal line in each multilink test set and a second electrical connection to an anode end of a last metal line in each multilink test set.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Ronald G. Filippi, Ping-Chuan Wang
  • Patent number: 7675378
    Abstract: Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kai D. Feng, Kafai Lai, Ping-Chuan Wang, Zhijian J. Yang
  • Patent number: 7671444
    Abstract: The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ping-Chuan Wang, Wai-Kin Li
  • Patent number: 7667328
    Abstract: An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anthony Kendall Stamper, Timothy Dooling Sullivan, Ping-Chuan Wang
  • Publication number: 20100039191
    Abstract: An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 18, 2010
    Applicant: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Jong-Ru Guo, Ping-Chuan Wang, Zhijian Yang
  • Publication number: 20100038747
    Abstract: An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Applicant: International Business Machines Corporation
    Inventors: Kaushik Chanda, Ronald G. Filippi, Joseph M. Lukaitis, Ping-Chuan Wang
  • Publication number: 20100025825
    Abstract: Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening to maintain the polished surface at the TSV structures and, thus, reliable conductivity to the BSM layer.
    Type: Application
    Filed: August 4, 2008
    Publication date: February 4, 2010
    Inventors: Danielle L. DeGraw, Peter James Lindgren, Da-Yuan Shih, Ping-Chuan Wang
  • Publication number: 20090311491
    Abstract: A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: Wu-Song Huang, Wai-kin Li, Ping-Chuan Wang
  • Publication number: 20090297759
    Abstract: Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 3, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kaushik Chanda, Ronald G. Filippi, Charles C. Goldsmith, Ping-Chuan Wang, Chih-Chao Yang
  • Publication number: 20090289368
    Abstract: An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.
    Type: Application
    Filed: August 3, 2009
    Publication date: November 26, 2009
    Applicant: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Ping-Chuan Wang, Yun-Yu Wang
  • Publication number: 20090283840
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Ephrem G. Gebreselasie, Zhong-Xiang He, Herbert Lei Ho, Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Robert Mark Rassel, John Matthew Safran, Kenneth Jay Stein, Norman Whitelaw Robson, Ping-Chuan Wang, Hongwen Yan
  • Publication number: 20090278260
    Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other.
    Type: Application
    Filed: May 6, 2008
    Publication date: November 12, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Conal E. Murray, Ping-Chuan Wang, Chih-Chao Yang
  • Patent number: 7609121
    Abstract: Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: October 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kai D. Feng, Kafai Lai, Ping-Chuan Wang, Zhijian J. Yang
  • Patent number: 7602265
    Abstract: The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: October 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Robert D. Edwards, Thomas J. Fleischman, Robert A. Groves, Charles J. Montrose, Richard P. Volant, Ping-Chuan Wang
  • Publication number: 20090243739
    Abstract: Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range.
    Type: Application
    Filed: May 2, 2008
    Publication date: October 1, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai D. Feng, Kafai Lai, Ping-Chuan Wang, Zhijian J. Yang
  • Publication number: 20090243738
    Abstract: Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Inventors: Kai D. Feng, Kafai Lai, Ping-Chuan Wang, Zhijian J. Yang
  • Publication number: 20090231025
    Abstract: A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level.
    Type: Application
    Filed: March 11, 2008
    Publication date: September 17, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ping-Chuan Wang, Jong-ru Guo, Louis L. Hsu, Zhijian Yang
  • Publication number: 20090200598
    Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 13, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang