Patents by Inventor Ping-Chuan Wang

Ping-Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8274301
    Abstract: An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kai D. Feng, Thomas J. Fleischman, Ping-Chuan Wang, Xiaojin Wei, Zhijian Yang
  • Publication number: 20120225549
    Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. HSU, Conal E. MURRAY, Ping-Chuan WANG, Chih-Chao YANG
  • Patent number: 8237286
    Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Ronald G. Filippi, Jong-Ru Guo, Ping-Chuan Wang
  • Patent number: 8237283
    Abstract: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chandra, Ronald G. Filippi, Wai-Lin Li, Ping-Chuan Wang, Chih-Chao Yang
  • Patent number: 8237278
    Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
  • Patent number: 8232115
    Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 8232646
    Abstract: An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Chao-Kun Hu, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
  • Publication number: 20120184076
    Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.
    Type: Application
    Filed: March 26, 2012
    Publication date: July 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
  • Publication number: 20120179943
    Abstract: A method for transmitting data from test device to a storage device via a parallel bus. The methods comprising the steps of setting a flag to indicate that data is available, reading the data, setting a flag to indicate the data was read. In addition test parameters are sent to the test device from the storage device, the method comprises the steps of checking to see if a test device is ready to receive data, transferring the test parameters, identifying the next channel to update.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Montrose, Ping-Chuan Wang
  • Publication number: 20120179409
    Abstract: A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Montrose, Ping-Chuan Wang
  • Publication number: 20120175612
    Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.
    Type: Application
    Filed: March 19, 2012
    Publication date: July 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 8211756
    Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
  • Publication number: 20120161334
    Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 28, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. HSU, Conal E. MURRAY, Ping-Chuan WANG, Chih-Chao YANG
  • Publication number: 20120156450
    Abstract: A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.
    Type: Application
    Filed: February 28, 2012
    Publication date: June 21, 2012
    Applicant: International Business Machines Corporation
    Inventors: Wu-Song Huang, Wai-kin Li, Ping-Chuan Wang
  • Publication number: 20120146186
    Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 14, 2012
    Applicant: International Business Machines Corporation
    Inventors: Joseph M. Lukaitis, Deborah M. Massey, Timothy D. Sullivan, Ping-Chuan Wang, Kimball M. Watson
  • Publication number: 20120146682
    Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/NĂ—2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 14, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Muthukumarasamy Karthikeyan, Yunsheng Song, Tso-Hui Ting, Richard P. Volant, Ping-Chuan Wang
  • Patent number: 8193575
    Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
  • Publication number: 20120126363
    Abstract: Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 24, 2012
    Applicant: International Business Machines Corporation
    Inventors: Ping-Chuan Wang, Chunyan E. Tian, Ronald Filippi, Wai-ki Li
  • Patent number: 8178945
    Abstract: Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p? substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p? substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ping-Chuan Wang, Robert C. Wong, Haining S. Yang
  • Publication number: 20120104610
    Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 3, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald Filippi, Ping-Chuan Wang, Griselda Bonilla, Kaushik Chanda, Robert D. Edwards, Andrew H. Simon