Patents by Inventor Ping-Chuan Wang
Ping-Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8889491Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.Type: GrantFiled: January 28, 2013Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Ronald G. Filippi, John A. Fitzsimmons, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
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Publication number: 20140332963Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.Type: ApplicationFiled: May 9, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Ronald G. Filippi, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
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Publication number: 20140332973Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.Type: ApplicationFiled: May 8, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Hanyi Ding, J. Edwin Hostetter, JR., Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20140332923Abstract: An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region.Type: ApplicationFiled: September 12, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Ronald G. Filippi, Erdem Kaltalioglu, Andrew T. Kim, Ping-Chuan Wang, Lijuan Zhang
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Publication number: 20140306322Abstract: A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface.Type: ApplicationFiled: April 11, 2013Publication date: October 16, 2014Applicant: International Business Machines CorporationInventors: Robert D. Edwards, Jeffrey P. Gambino, Charles F. Musante, Ping-Chuan Wang
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Patent number: 8853693Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.Type: GrantFiled: March 19, 2012Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
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Patent number: 8815669Abstract: A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.Type: GrantFiled: February 25, 2013Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Jin Cai, Chengwen Pei, Robert R. Robison, Ping-Chuan Wang
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Publication number: 20140234990Abstract: A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: International Business Machines CorporationInventors: Kai D. Feng, J. Edwin Hostetter, JR., Ping-Chuan Wang, Zhijian Yang
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Publication number: 20140217612Abstract: An electronic fuse structure including an Mx level comprising an Mx metal, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, where the Mx+1 metal comprises a thick portion and a thin portion, and where the Mx metal, the Mx+1 metal, and the via are substantially filled with a conductive material.Type: ApplicationFiled: February 6, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Erdem Kaltalioglu, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang, Lijuan Zhang
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Publication number: 20140203436Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.Type: ApplicationFiled: August 12, 2013Publication date: July 24, 2014Applicant: International Business Machines CorporationInventors: Ronald G. Filippi, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 8779838Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.Type: GrantFiled: October 25, 2011Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Zhijian Yang, Ping-Chuan Wang, Kai D. Feng, Edwin J. Hostetter, Jr.
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Patent number: 8765568Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.Type: GrantFiled: October 8, 2013Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Joseph M. Lukaitis, Deborah M. Massey, Timothy D. Sullivan, Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20140177373Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Applicant: International Business Machines CorporationInventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin LI, Ping-Chuan Wang
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Patent number: 8759175Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.Type: GrantFiled: March 26, 2012Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
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Patent number: 8759152Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.Type: GrantFiled: June 6, 2012Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
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Publication number: 20140167772Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: ApplicationFiled: February 25, 2014Publication date: June 19, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Publication number: 20140159775Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.Type: ApplicationFiled: January 16, 2014Publication date: June 12, 2014Applicant: International Business Machines CorporationInventors: Kai D. Feng, Jong-ru Guo, Trushill N. Shah, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20140152337Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
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Patent number: 8742766Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: GrantFiled: September 30, 2013Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 8742782Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.Type: GrantFiled: July 27, 2011Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Xu Ouyang, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin