Patents by Inventor Ping-Chuan Wang
Ping-Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability
Patent number: 8465657Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.Type: GrantFiled: August 3, 2007Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Kaushik Chanda, James J. Demarest, Ronald G. Filippi, Roy C. Iggulden, Edward W. Kiewara, Ping-Chuan Wang, Yun-Yu Wang -
Patent number: 8455351Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.Type: GrantFiled: June 22, 2012Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Ronald G. Filippi, Jong-Ru Guo, Ping-Chuan Wang
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Patent number: 8450205Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.Type: GrantFiled: May 17, 2012Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Conal E. Murray, Ping-Chuan Wang, Chih-Chao Yang
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Patent number: 8446014Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.Type: GrantFiled: June 22, 2012Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Ronald G. Filippi, Jong-Ru Guo, Ping-Chuan Wang
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Publication number: 20130106455Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Publication number: 20130099853Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.Type: ApplicationFiled: October 25, 2011Publication date: April 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhijian Yang, Ping-Chuan Wang, Kai D. Feng, Edwin J. Hostetter, JR.
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Patent number: 8422322Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: GrantFiled: November 3, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
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Patent number: 8420537Abstract: Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.Type: GrantFiled: May 28, 2008Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Ronald G. Filippi, Charles C. Goldsmith, Ping-Chuan Wang, Chih-Chao Yang
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Patent number: 8378447Abstract: An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.Type: GrantFiled: April 13, 2011Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Ronald G. Filippi, Joseph M. Lukaitis, Ping-Chuan Wang
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Publication number: 20130027051Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xu Ouyang, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 8349723Abstract: An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.Type: GrantFiled: January 3, 2012Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Ronald Filippi, Wai-kin Li, Ping-Chuan Wang
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Publication number: 20120292763Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.Type: ApplicationFiled: August 2, 2012Publication date: November 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald G. Filippi, John A. Fitzsimmons, Kevin Kolvenbach, Ping-Chuan Wang
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Patent number: 8304863Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.Type: GrantFiled: February 9, 2010Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Ronald G. Filippi, John A. Fitzsimmons, Kevin Kolvenbach, Ping-Chuan Wang
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Publication number: 20120273966Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.Type: ApplicationFiled: June 22, 2012Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi Ding, Ronald G. Filippi, Jong-Ru Guo, Ping-Chuan Wang
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Patent number: 8299809Abstract: An apparatus is provided and includes a thermally isolated device under test to which first and second voltages are sequentially applied, a local heating element to impart first and second temperatures to the device under test substantially simultaneously while the first and second voltages are sequentially applied, respectively and a temperature-sensing unit to measure the temperature of the device under test.Type: GrantFiled: September 21, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Tso-Hui Ting, Ping-Chuan Wang, Mohammed I. Younus
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Patent number: 8299567Abstract: Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.Type: GrantFiled: November 23, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Ping-Chuan Wang, Chunyan E Tian, Ronald Filippi, Wai-kin Li
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Publication number: 20120264289Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi Ding, Ronald G. Filippi, Jong-Ru Guo, Ping-Chuan Wang
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Publication number: 20120264295Abstract: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chandra, Ronald G. Filippi, Wai-Kin Li, Ping-Chuan Wang, Chih-Chao Yang
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Publication number: 20120249159Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: ApplicationFiled: March 29, 2011Publication date: October 4, 2012Applicant: International Business Machines CorporationInventors: Ronald G. Filippi, Griselda Bonilla, Kaushik Chanda, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Publication number: 20120241977Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.Type: ApplicationFiled: June 6, 2012Publication date: September 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang