Abstract: The present disclosure provides a semiconductor device, a semiconductor structure and a formation method thereof, and relates to the field of semiconductor technologies. The formation method includes: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer to form trenches and through holes distributed side by side in the sacrificial layer; forming insulating layers covering a sidewall of the trench and a sidewall of the through hole; sequentially forming a conductive layer and a passivation layer in the trench and the through hole to form a bitline structure in the trench; and removing the passivation layer in the through hole to form a capacitor contact structure in the through hole.

Abstract: A switch short-circuited diagnosis method includes steps of: determining an initial voltage interval of multiple voltage intervals according to voltage relationships between voltages of a first phase wire, a second phase wire, and a third phase wire; performing a switch short-circuited diagnosis of a first bidirectional switch module in the three consecutive voltage intervals from the initial voltage interval, and including steps of: turning on a first switch branch, a second switch branch, or a third switch branch of the first bidirectional switch module according to the voltage relationships between the voltages of the first, second and third phase wires, determining whether an overcurrent occurs to diagnose whether the first switch branch, the second switch branch, or the third switch branch of the first bidirectional switch module is in a short-circuited state, and performing the switch short-circuited diagnosis for the next voltage interval.

Abstract: A conductive structure includes: a conductive pillar and at least one embedded block arranged in the conductive pillar, a coefficient of thermal expansion of the embedded block being less than that of the conductive pillar. When the conductive pillar is heated and expanded, an extrusion effect of the conductive pillar on a structure adjacent to the conductive pillar can be reduced, thereby improving the performance of the semiconductor structure.

Abstract: A semiconductor structure includes a base, a conductive pillar at least located in the base, connecting structures and an electrical connection layer. At least one connecting structure is electrically connected to an end of the conductive pillar, the material of the connecting structure is different from that of the conductive pillar, and a total area of an orthographic projection of the connecting structure on the base is less than an area of an orthographic projection of the conductive pillar on the base. The electrical connection layer is electrically connected to an end of the connecting structure distal from the conductive pillar.

Abstract: A semiconductor apparatus includes a substrate and a through silicon via (TSV) structure; a groove is disposed on the substrate; the TSV structure is disposed on the substrate; and a first end of the TSV structure is exposed in the groove, and a distance between an end surface of the first end and a bottom wall of the groove is smaller than the depth of the groove. The first end of the TSV structure is exposed so as to facilitate heat dissipation; the distance between the end surface of the first end and the bottom wall of the groove is smaller than the depth of the groove, i.e., the first end of the TSV structure is sunken in the groove, and other structures will not be affected.

Abstract: A forming method for an opening structure includes: a substrate is provided, where a target layer is formed in the substrate, and the substrate exposes a surface of the target layer; an annular gasket is formed on the surface of the target layer, where a central through hole exposing a part of the surface of the target layer is provided in a center of the annular gasket; a dielectric layer covering the substrate, the target layer and the annular gasket is formed; and the dielectric layer is etched to form an etching hole communicating with the central through hole in the dielectric layer, where the etching hole and the central through hole form an opening structure.

Abstract: A capacitance structure and a forming method thereof are provided, and the forming method includes: an annular gasket is formed on a substrate, and after a central through hole exposing a part of a surface of the substrate is formed in a center of the annular gasket, a first capacitance structure is formed in the central through hole; a dielectric layer covering the substrate, the annular gasket and the first capacitance structure is formed; the dielectric layer is etched to form an etching hole communicating with the central through hole in the dielectric layer; and a second capacitance structure connected to the first capacitance structure is formed in the etching hole.

Abstract: A semiconductor structure includes: a base; a conductive column, which is at least located in the base; an electric connection layer, which is connected to an end part of the conductive column. The end part, towards the electric connection layer, of the conductive column has a first protruding part and at least one groove defined by the first protruding part, the electric connection layer has a second protruding part at a position corresponding to the groove, and the second protruding part is embedded in the groove.

Abstract: A semiconductor structure includes: a substrate and a dielectric layer arranged on the substrate; a conductive plug, a first portion of the conductive plug being arranged in the substrate, and a second portion of the conductive plug being arranged in the dielectric layer; and a capacitor array, the capacitor array at least surrounding the second portion of the conductive plug.

Abstract: A method of clamping an output current of a three-phase power converter is provided. The three-phase power converter includes three switching bridge arms and provides a three-phase output voltage command, and each switching bridge arm has an upper switch and a lower switch connected in series. The method includes steps of: determining that the output current is greater than a first current threshold to activate a current clamping control procedure, comparing a carrier signal with the three-phase output voltage command to turn on the lower switches by a first zero vector when the carrier signal is rising and turn on the upper switches by a second zero vector when the carrier signal is falling, determining that the output current is greater than a second current threshold to activate an overcurrent protection procedure, wherein the second current threshold is greater than the first current threshold.

Abstract: The present disclosure relates to a package substrate comprising: a substrate having opposing first surface and second surface; at least one vent hole extending through the first surface and the second surface of the substrate, the vent hole comprising at least a long-strip hole.

Abstract: A semiconductor structure and a forming method thereof are provided. The method of forming the semiconductor structure includes: providing a wafer having a front surface and a back surface opposite to the front surface; patterning the back surface of the wafer to form a groove extending from the back surface towards the front surface; forming a dielectric layer at a bottom and a side wall of the groove; and forming, on the dielectric layer, a conductive layer filling the groove.

Abstract: A contact window structure, a metal plug and a forming method thereof, a method of forming the contact window structure and a semiconductor structure are provided. In the method of forming the contact window, an annular pad is formed on a surface of a target layer. A central via, from which partial surface of the target layer is exposed, is formed in the middle part of the annular pad. A dielectric layer covering a substrate, the target layer and the annular pad is formed. The dielectric layer is etched to form an etch hole connected to the central via in the dielectric layer. The annular pad is removed along the etch hole and the central via to enlarge a size of the central via, so as to form the contact window structure by the etch hole and the central via with the enlarged size.

Abstract: A semiconductor structure is provided, including: a substrate and a dielectric layer arranged on the substrate; a conductive plug, wherein a first part of the conductive plug is arranged in the substrate, and a second part of the conductive plug is arranged in the dielectric layer; and an isolation ring structure at least surrounding the second part of the conductive plug.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes at least two electrode layers, and the electrode layers are parallel to each other and arranged in different layers. Adjacent electrode layers overlap with each other and have an overlapping area, a dielectric layer is arranged between the adjacent electrode layers, and an air gap is arranged in the dielectric layer located in the overlapping area.

Abstract: A contact window structure and a method for forming the contact window structure are provided. The method includes: an etching spacer is formed on a surface of a target layer, and a dielectric layer covering a substrate, the target layer and the etching spacer is formed; the dielectric layer is etched to form an etching hole in the dielectric layer, a bottom of the etching hole exposing a top surface of the etching spacer; and the etching spacer is removed along the etching hole to form an etching channel communicating with the etching hole, the etching channel exposing a portion of the surface of the target layer and constituting a contact window structure with the etching hole.

Abstract: A switch short-circuited diagnosis method includes steps of: determining an initial voltage interval of multiple voltage intervals according to voltage relationships between voltages of a first phase wire, a second phase wire, and a third phase wire; performing a switch short-circuited diagnosis of a first bidirectional switch module in the three consecutive voltage intervals from the initial voltage interval, and including steps of: turning on a first switch branch, a second switch branch, or a third switch branch of the first bidirectional switch module according to the voltage relationships between the voltages of the first, second and third phase wires, determining whether an overcurrent occurs to diagnose whether the first switch branch, the second switch branch, or the third switch branch of the first bidirectional switch module is in a short-circuited state, and performing the switch short-circuited diagnosis for the next voltage interval.

Abstract: A matrix power conversion device including a plurality of three-phase switching modules and a controller is provided. Each three-phase switching module includes a plurality of bidirectional switches connected to the input phase voltages of the three-phase input power respectively and outputs a corresponding output phase voltage of the three-phase output power. The controller determines a maximum voltage, an intermediate voltage and a minimum voltage among all the input phase voltages to acquire a waveform of a control carrier wave in a switching cycle. The controller acquires output expected values corresponding to all output phase voltages and compares them with the waveform of the control carrier wave for acquiring a turning-on time of each of the plurality of bidirectional switches. Accordingly, the controller controls the matrix power conversion device to switch the three-phase input power so as to change the three-phase output power for driving the motor.

Abstract: The present disclosure relates to a redistribution layer (RDL) structure, a manufacturing method thereof, and a semiconductor structure having the same. The RDL structure includes an RDL, disposed on a substrate, and including a bond pad portion and a wire portion connected to the bond pad portion, where a thickness of the bond pad portion is greater than a thickness of the wire portion.

Abstract: A method of controlling a power converter is provided. The power converter generates a three-phase output power by switching an input power through a plurality of switches. The method includes steps of: acquiring a three-phase output command corresponding to the three-phase output power; comparing the three-phase output command with a control carrier to acquire a voltage phase angle corresponding to the three-phase output command; acquiring a three-phase current value of the three-phase output power; detecting the voltage phase angle and a positive/negative change of the three-phase current value to decide a zero-sequence voltage; composing the zero-sequence voltage and the three-phase output command to acquire a three-phase output expected value; comparing the three-phase expected values with the control carrier to acquire a turned-on time of each switch; and switching the input power to adjust the three-phase output power according to the turned-on time of each switch.