Abstract: A power system includes a pulse width modulation device. The pulse width modulation device outputs first, second, third and fourth driving signals. The pulse width modulation device receives a control signal. The control signal is divided into a positive periodic signal and a negative periodic signal. A portion of the positive periodic signal higher than or equal to a maximum threshold voltage is clamped as the maximum threshold voltage to generate a first comparison waveform. The positive periodic signal is clamped as the reference voltage level to generate a second comparison waveform. According to the first comparison waveform, a first ramp signal is generated. According to the second comparison waveform, a first pulse width modulation signal is generated. The first, second, third and fourth driving signals are adjusted according to the first ramp signal and the first pulse width modulation signal.

Abstract: A semiconductor structure includes a base, a conductive pillar at least located in the base, connecting structures and an electrical connection layer. At least one connecting structure is electrically connected to an end of the conductive pillar, the material of the connecting structure is different from that of the conductive pillar, and a total area of an orthographic projection of the connecting structure on the base is less than an area of an orthographic projection of the conductive pillar on the base. The electrical connection layer is electrically connected to an end of the connecting structure distal from the conductive pillar.

Abstract: A semiconductor structure includes: a base; a conductive column, which is at least located in the base; an electric connection layer, which is connected to an end part of the conductive column. The end part, towards the electric connection layer, of the conductive column has a first protruding part and at least one groove defined by the first protruding part, the electric connection layer has a second protruding part at a position corresponding to the groove, and the second protruding part is embedded in the groove.

Abstract: A semiconductor device manufacturing method includes: providing a substrate having a memory cell array area; forming a word line trench; forming a word line conductive layer in the word line trench; forming a photoresist on the substrate surface, and patterning it to protect the word line conductive layer in the contact areas but exposes the word line conductive layer outside the word line contact area, and etching the conductive layer. The resulting thickness of the word line conductive structure in the word line contact area is greater than outside the word line contact area. Thereby the opening of the word line contact hole is reduced. The depth of the window position reduces the process time in forming the contact hole, which reduces the excessive erosion of the sidewalls of contact hole having a shallower opening depth, so to avoid the device short circuit.

Abstract: A capacitance structure and a forming method thereof are provided, and the forming method includes: an annular gasket is formed on a substrate, and after a central through hole exposing a part of a surface of the substrate is formed in a center of the annular gasket, a first capacitance structure is formed in the central through hole; a dielectric layer covering the substrate, the annular gasket and the first capacitance structure is formed; the dielectric layer is etched to form an etching hole communicating with the central through hole in the dielectric layer; and a second capacitance structure connected to the first capacitance structure is formed in the etching hole.

Abstract: A semiconductor apparatus includes a substrate and a through silicon via (TSV) structure; a groove is disposed on the substrate; the TSV structure is disposed on the substrate; and a first end of the TSV structure is exposed in the groove, and a distance between an end surface of the first end and a bottom wall of the groove is smaller than the depth of the groove. The first end of the TSV structure is exposed so as to facilitate heat dissipation; the distance between the end surface of the first end and the bottom wall of the groove is smaller than the depth of the groove, i.e., the first end of the TSV structure is sunken in the groove, and other structures will not be affected.

Abstract: A forming method for an opening structure includes: a substrate is provided, where a target layer is formed in the substrate, and the substrate exposes a surface of the target layer; an annular gasket is formed on the surface of the target layer, where a central through hole exposing a part of the surface of the target layer is provided in a center of the annular gasket; a dielectric layer covering the substrate, the target layer and the annular gasket is formed; and the dielectric layer is etched to form an etching hole communicating with the central through hole in the dielectric layer, where the etching hole and the central through hole form an opening structure.

Abstract: The present disclosure provides a semiconductor device, a semiconductor structure and a formation method thereof, and relates to the field of semiconductor technologies. The formation method includes: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer to form trenches and through holes distributed side by side in the sacrificial layer; forming insulating layers covering a sidewall of the trench and a sidewall of the through hole; sequentially forming a conductive layer and a passivation layer in the trench and the through hole to form a bitline structure in the trench; and removing the passivation layer in the through hole to form a capacitor contact structure in the through hole.

Abstract: A conductive structure includes: a conductive pillar and at least one embedded block arranged in the conductive pillar, a coefficient of thermal expansion of the embedded block being less than that of the conductive pillar. When the conductive pillar is heated and expanded, an extrusion effect of the conductive pillar on a structure adjacent to the conductive pillar can be reduced, thereby improving the performance of the semiconductor structure.

Abstract: A contact window structure, a metal plug and a forming method thereof, a method of forming the contact window structure and a semiconductor structure are provided. In the method of forming the contact window, an annular pad is formed on a surface of a target layer. A central via, from which partial surface of the target layer is exposed, is formed in the middle part of the annular pad. A dielectric layer covering a substrate, the target layer and the annular pad is formed. The dielectric layer is etched to form an etch hole connected to the central via in the dielectric layer. The annular pad is removed along the etch hole and the central via to enlarge a size of the central via, so as to form the contact window structure by the etch hole and the central via with the enlarged size.

Abstract: A contact window structure and a method for forming the contact window structure are provided. The method includes: an etching spacer is formed on a surface of a target layer, and a dielectric layer covering a substrate, the target layer and the etching spacer is formed; the dielectric layer is etched to form an etching hole in the dielectric layer, a bottom of the etching hole exposing a top surface of the etching spacer; and the etching spacer is removed along the etching hole to form an etching channel communicating with the etching hole, the etching channel exposing a portion of the surface of the target layer and constituting a contact window structure with the etching hole.

Abstract: A semiconductor structure includes: a substrate and a dielectric layer arranged on the substrate; a conductive plug, a first portion of the conductive plug being arranged in the substrate, and a second portion of the conductive plug being arranged in the dielectric layer; and a capacitor array, the capacitor array at least surrounding the second portion of the conductive plug.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes at least two electrode layers, and the electrode layers are parallel to each other and arranged in different layers. Adjacent electrode layers overlap with each other and have an overlapping area, a dielectric layer is arranged between the adjacent electrode layers, and an air gap is arranged in the dielectric layer located in the overlapping area.

Abstract: A bonding pad structure includes a bonding pad layer, and an expansion stagnating block that is at least wrapped by the bonding pad layer partially. The expansion stagnating block is subjected to high-temperature tempering treatment. A semiconductor structure, a semiconductor package structure and a method for preparing the same are also provided.

Abstract: A semiconductor structure and a forming method thereof are provided. The forming method of the semiconductor structure includes that: a wafer having a front surface and a back surface is provided, a conductive plug being provided in the wafer, the conductive plug extending from the front surface to the back surface and the conductive plug having a bottom surface located in the wafer; an etching process is performed on the back surface of the wafer to form a groove exposing at least the bottom surface of the conductive plug; and a functional layer covering the bottom surface of the conductive plug is formed.

Abstract: A semiconductor structure and a forming method thereof are provided. The method of forming the semiconductor structure includes: providing a wafer having a front surface and a back surface opposite to the front surface; patterning the back surface of the wafer to form a groove extending from the back surface towards the front surface; forming a dielectric layer at a bottom and a side wall of the groove; and forming, on the dielectric layer, a conductive layer filling the groove.

Abstract: A semiconductor structure is provided, including: a substrate and a dielectric layer arranged on the substrate; a conductive plug, wherein a first part of the conductive plug is arranged in the substrate, and a second part of the conductive plug is arranged in the dielectric layer; and an isolation ring structure at least surrounding the second part of the conductive plug.

Abstract: A semiconductor device is disclosed. The device includes a stacked structure and an electrode. The stacked structure includes at least one die, the electrode is located on a side surface of the stacked structure, and the electrode has a length greater than or equal to a thickness of the die in a thickness direction of the die. The semiconductor device does not need a micro-bump for connection, thereby allowing a thinner stacked structure. The electrodes are disposed on the side surface of the stacked structure. Thus, it is not necessary to provide a connection at the wiring layer or reserve connection position when designing the circuit. The length of the electrode in the thickness direction of the die is greater than or equal to the thickness of the die, facilitating the connection of circuits on a plurality of dies.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a semiconductor substrate including island patterns and trenches alternately arranged in a semiconductor substrate, wherein an upper surface of the island pattern close to a corresponding one of the trenches is a corner area; a patterned liner oxide layer covering an area of the upper surface of the island pattern except the corner area; and a protective layer covering the sidewalls and the bottom surface of the trench, the corner area and the side surface of the patterned liner oxide layer, wherein the protective layer extends from the sidewall of the trench to the corner area to form a corner; and an isolation structure located within each of the trenches. An area of the island pattern near the corner may be prevented from being oxidized.

Abstract: The present disclosure relates to a redistribution layer (RDL) structure, a manufacturing method thereof, and a semiconductor structure having the same. The RDL structure includes an RDL, disposed on a substrate, and including a bond pad portion and a wire portion connected to the bond pad portion, where a thickness of the bond pad portion is greater than a thickness of the wire portion. According to the RDL structure provided by the present disclosure, a bond pad portion has a thickness greater than a wire portion, so that the thicker bond pad portion can provide more impact buffer areas in gold or copper wire bonding of packaging to prevent a substrate from breaking due to a stress, and prevent an increase in a parasitic capacitance between wires.