Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.

Abstract: A semiconductor package is provided and includes: an insulative layer having opposing first and second surfaces; a wiring layer embedded in the insulative layer and having a first side that is exposed from the first surface of the insulative layer and a second side opposing the first side and attached to the second surface of the insulative layer; at least one electronic component mounted on the second side of the wiring layer and electrically connected to the wiring layer; and an encapsulating layer formed on the second side of the wiring layer and the second surface of the insulative layer and encapsulating the electronic component. Therefore, the single wiring layer is allowed to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path.

Abstract: An inductor structure is provided. A plurality of first and second conductive posts have end surfaces corresponding in profile to ends of first conductive sheets, respectively. As such, the profiles of the end surfaces of the first and second conductive posts are non-cylindrical so as to increase the contact area between the first conductive sheets and the first and second conductive posts, thereby improving the conductive quality and performance of the inductor. Further, since the first and second conductive posts are formed by stacking a plurality of post bodies on one another, the number and cross-sectional area of loops are increased so as to increase the inductance value. A method for fabricating the inductor structure, an electronic package and a fabrication method thereof, and a method for fabricating a packaging carrier are further provided.

Abstract: A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m·k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board.

Abstract: A semiconductor package structure includes a chip, a first conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with a first metal electrode pad and a second side with a second metal electrode pad. The first conductive pillar is disposed adjacent to the chip. The dielectric layer covers the chip and the first conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the first conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the first conductive pillar. The second patterned conductive layer is disposed on a first surface of the dielectric.

Abstract: A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.

Abstract: Data transmission method of server firmware adapted to a server having request end firmware devise, server end firmware devise and shared memory, with the method comprises: putting a request into the shared memory via http/https by the request end firmware devise, obtaining the request from the shared memory by the server end firmware devise from the shared memory, storing a requested data file and a completion notification into the shared memory via http/https according to the request by the server end firmware devise when the request is determined as conforming to a request rule by the server end firmware devise, wherein the completion notification is marked as success when the request content is accord with a request rule, and obtaining the requested data file from the shared memory when the completion notification is received and determined as success by the request end firmware devise.

Abstract: Data transmission method of server firmware adapted to a server having request end firmware devise, server end firmware devise and shared memory, with the method comprises: putting a request into the shared memory via http/https by the request end firmware devise, obtaining the request from the shared memory by the server end firmware devise from the shared memory, storing a requested data file and a completion notification into the shared memory via http/https according to the request by the server end firmware devise when the request is determined as conforming to a request rule by the server end firmware devise, wherein the completion notification is marked as success when the request content is accord with a request rule, and obtaining the requested data file from the shared memory when the completion notification is received and determined as success by the request end firmware devise.

Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.

Abstract: A key scanning method and an input device thereof are provided. The key scanning method for an input device with at least a first key group and a subsidiary key group comprises: triggering a first main scan line electrically connected to the first key group and reading electrical signals received via a plurality of signal sensing lines electrically connected to the first key group to determine whether any said key among the first key group is triggered; and triggering a non-triggered one of a plurality of subsidiary scan lines electrically connected to the subsidiary key group and reading electrical signals received via another plurality of signal sensing lines electrically connected to the subsidiary key group to determine whether any said key among the subsidiary key group is triggered, wherein the first main scan line and the subsidiary scan lines are triggered one after another for multiple times.

Abstract: A semiconductor packaging substrate and a method for fabricating the same are provided. The method includes forming a solder resist structure having a hole on a circuit structure, with a portion of the circuit structure exposed from the hole, and forming a cup-shaped solder stand on the exposed circuit layer and a hole wall of the hole. During a packaging process, the design of the solder stand increases a contact area of a solder tin ball with a metal material. Therefore, a bonding force between the solder tin ball and the solder stand is increased, and the solder tin ball can be protected from being broken or fell off. An electronic package having the semiconductor packaging substrate and a method for fabricating the electronic package are also provided.

Abstract: A method for fabricating the semiconductor device includes providing a substrate, forming a bottom conductive plug on the substrate, forming a semiconductor layer on the bottom conductive plug, rounding a top surface of the semiconductor layer, turning the semiconductor layer into an intervening conductive layer, and forming a top conductive plug on the intervening conductive layer

Abstract: An active fluid static elimination system installed in a fluid transportation pipeline includes a solenoid valve, an electrostatic measuring device, a fluid destaticizer, and a controller. The solenoid valve is connected to a connecting port of the fluid transportation pipeline, and the electrostatic measuring device is used to measure an electrostatic value of a fluid in the fluid transportation pipeline. The fluid destaticizer is connected to the solenoid valve, and the controller is connected to the electrostatic measuring device and the solenoid valve. The solenoid valve is opened to allow the fluid passing through the fluid destaticizer to eliminate the electrostatic charge of the fluid when the controller determines that the electrostatic value measured by the electrostatic measuring device is greater than a predetermined value.

Abstract: A brush roller and its manufacturing method and brush roller mold is provided, the brush roller is manufactured by foaming a gaseous pore filler, while solving the problem of using a solid pore filler foaming method to manufacture the brush roller. In addition, the brush roller of the present invention has a plurality of fluid channels communicating between any adjacent two, and the plurality of fluid channels respectively extend to the surface of the brush roller to form pores to improve the fluid permeability of the brush roller, and in the brush roller manufacturing method of the present invention, after the PVA emulsified solution is cured, the compressive stress under the condition of the predetermined compression ratio can be formed to meet the expected brush roller, and it can be used to brush the circuit substrate.

Abstract: A key scanning method, a scan method for a key scan circuit, and an input device thereof are provided. The key scanning method comprises performing a first scan procedure which includes triggering a first main scan line and reading electrical signals received via a plurality of signal sensing lines to determine whether any of the keys among a first key group is triggered. Then, performing a second scan procedure which includes triggering at least one of a plurality of secondary scan lines and reading the electrical signals received via the plurality of signal sensing lines to determine whether any of the keys among a second key group is triggered. In the key scanning method, the first scan procedure and the second scan procedure are performed one after another, and each of the secondary scan lines is triggered at least once.

Abstract: The present application discloses a method for fabricating a semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled. method includes providing an active interposer comprising a programmable unit; providing a first logic die and bonding a first side of the active interposer onto the first logic die; providing a first memory die comprising a storage unit; and bonding the first memory die onto a second side of the active interposer, wherein the second side of the active interposer is parallel to the first side of the active interposer.

Abstract: A photosensitive electrically conductive structure includes: a substrate; a releasing photosensitizing resin layer disposed on the substrate; a nano silver layer disposed on the releasing photosensitizing resin layer; and a photosensitive electrically conductive layer disposed on an edge of the nano silver layer. A visible region is defined in the photosensitive electrically conductive structure where the nano silver layer is not covered by the photosensitive electrically conductive layer and a peripheral wiring region is defined in the photosensitive electrically conductive structure where the nano silver layer is covered by the photosensitive electrically conductive layer. The releasing photosensitizing resin layer has an average molecular weight (Mn) greater than 3,000 but less than 100,000, and the releasing photosensitizing resin layer, the nano silver layer, and the photosensitive electrically conductive layer are patterned.

Abstract: The present application relates to a semiconductor device with an intervening layer and a method for fabricating the semiconductor device with the intervening layer. The semiconductor device includes a substrate, a bottom conductive plug positioned on the substrate, an intervening conductive layer positioned on the bottom conductive plug, and a top conductive plug positioned on the intervening conductive layer. A top surface of the intervening conductive layer is non-planar.

Abstract: A package apparatus comprises a first wiring layer, a first dielectric material layer, a first conductive pillar layer, a first buffer layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to the first surface. The first dielectric material layer is disposed within partial zone of the first wiring layer. The first conductive pillar layer is disposed on the second surface of the first wiring layer. The first buffer layer is disposed within partial zone of the first conductive pillar layer. The second wiring layer is disposed on the first buffer layer and one end of the first conductive pillar layer. The protection layer is disposed on the first buffer layer and the second wiring layer.

Abstract: A package structure for a semiconductor device includes a first conductive layer, a second conductive layer, a first die, a second die, a plurality of first blind via pillars and a conductive structure. The first conductive layer has a first surface and a second surface. The first die and the second die respectively have an active surface and a back surface, which are disposed opposite to each other. There is a plurality of metal pads disposed on the active surface. The first die is attached to the first surface of the first conductive layer with its back surface, and the second die is attached to the second surface of the first conductive layer with its back surface. The first and second conductive layers, the first and second dies, the first blind hole pillars and conductive structure are covered by a dielectric material.