Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.

Abstract: The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

Abstract: A memory array and a method for preparing the memory are provided. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

Abstract: A floating image generation device is disclosed, which includes a light source, a first image forming unit, a second image forming unit, a floating image generation unit, and a transflective layer. The first image forming unit is disposed on the light source. The second image forming unit is disposed on the first image forming unit. The floating image generation unit is disposed on the second image forming unit. The transflective layer is disposed between the first image forming unit and the second image forming unit. The light source is capable of transmitting a first light to pass through the first image forming unit, the second image forming unit, the floating image generation unit, and the transflective layer for generating a floating image. At least a portion of a second light from the other side of the floating image generation unit is reflected by the transflective layer for generating a flat image.

Abstract: A floating image generation device is disclosed, which includes a light source, an image generation module, and a floating image generation unit. The image generation module is disposed above the light source and includes a shading unit and an image generation unit. The shading unit is capable of changing light transmissivity state. The image generation unit is disposed above the shading unit. The floating image generation unit is disposed above the image generation unit. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a first floating image when the shading unit is in a first light transmissivity state. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a second floating image when the shading unit is in a second light transmissivity state.

Abstract: A method of manufacturing a semiconductor memory device includes providing a substrate with a drain, a source and a gate structure disposed on the substrate between the drain and the source; forming a first inter-layer dielectric covering the substrate and the gate structure; forming a plug in the first inter-layer dielectric, with a first part contacting the source of the substrate. In the next step, a second part of the plug is exposed through the first inter-layer dielectric, and a storage node landing pad is formed on the exposed second part of the plug; a second inter-layer dielectric is formed on the first inter-layer dielectric, covering the storage node landing pad; a bit line is formed, connected to the substrate through the second inter-layer dielectric and the first inter-layer dielectric; a third inter-layer dielectric is formed on the bit line; and, a storage node is formed on the third inter-layer dielectric.

Abstract: The present application relates to a semiconductor device with an intervening layer and a method for fabricating the semiconductor device with the intervening layer. The semiconductor device includes a substrate, a bottom conductive plug positioned on the substrate, an intervening conductive layer positioned on the bottom conductive plug, and a top conductive plug positioned on the intervening conductive layer. A top surface of the intervening conductive layer is non-planar.

Abstract: The disclosure provides an Internet of things device and a battery power supply circuit thereof. A voltage of a battery is compared with a predetermined over-discharge voltage to generate a comparison signal. A battery protection circuit serves as a power supply path from the battery to a load and determines whether to cut off the power supply path according to the comparison signal. The battery protection circuit cuts off the power supply path when the voltage of the battery decreases from a value greater than the predetermined over-discharge voltage to a value less than the predetermined over-discharge voltage, but does not turn on the power supply path when the voltage of the battery increases from a value less than the predetermined over-discharge voltage to a value greater than the predetermined over-discharge voltage.

Abstract: The present application discloses a method for fabricating a semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled. method includes providing an active interposer comprising a programmable unit; providing a first logic die and bonding a first side of the active interposer onto the first logic die; providing a first memory die comprising a storage unit; and bonding the first memory die onto a second side of the active interposer, wherein the second side of the active interposer is parallel to the first side of the active interposer.

Abstract: A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar.

Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.

Abstract: The present application discloses a method for fabricating a semiconductor device with liners. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, inwardly forming a trench on the first surface of the substrate, forming a plurality of liners positioned on side surfaces of the trench, forming a first insulating segment filling the trench, and removing part of the substrate from the second surface to expose the first insulating segment and the plurality of liners.

Abstract: A flip-chip package substrate is provided. A strengthening structure is provided on one side of a circuit structure to increase the rigidity of the flip-chip package substrate. When the flip-chip package substrate is used in large-scale packaging, the flip-chip package substrate can have good rigidity, so that the electronic package can be prevented from warping.

Abstract: A photosensitive electrically conductive structure includes: a substrate; a releasing photosensitizing resin layer disposed on the substrate; a nano silver layer disposed on the releasing photosensitizing resin layer; and a photosensitive electrically conductive layer disposed on an edge of the nano silver layer. A visible region is defined in the photosensitive electrically conductive structure where the nano silver layer is not covered by the photosensitive electrically conductive layer and a peripheral wiring region is defined in the photosensitive electrically conductive structure where the nano silver layer is covered by the photosensitive electrically conductive layer. The releasing photosensitizing resin layer has an average molecular weight (Mn) greater than 3,000 but less than 100,000, and the releasing photosensitizing resin layer, the nano silver layer, and the photosensitive electrically conductive layer are patterned.

Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.

Abstract: An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled.

Abstract: Compositions and methods for increasing recovery, or flowback, of hydrocarbon compounds from hydrocarbon-containing subterranean oil formations. Concentrates include a sulfonated and/or a sulfated surfactant, an alkoxylated alcohol surfactant, a coupling agent, a hydrotrope, an additional surfactant, and water. Injectate compositions for oil recovery include the concentrate and a water source such as a produced water and/or seawater. Inclusion of particular hydrotropes such as sodium xylene sulfonate and/or potassium toluene phosphate in the compositions provides higher yields of hydrocarbons recovered. Larger amounts of hydrotrope result in an increase in injectate interfacial tension, but also result, as judged by decreased turbidity, in improved compatibility of the surfactant system in injectates made with water sources comprising salts.

Abstract: A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.

Abstract: A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.