Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact and a first bonding alignment mark. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact and a second bonding alignment mark. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface.

Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact.

Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact.

Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a contact hole region at a front side of a first substrate; forming a semiconductor structure at the front side of the first substrate and the semiconductor structure having a first conductive contact, forming a recess at a backside of the first substrate to expose at least a portion of the dielectric layer; and forming a second conductive layer above the exposed dielectric layer to connect the first conductive contact. The 3D integrated wiring structure can include a first substrate having a contact hole region; a dielectric layer disposed in the contact hole region; a semiconductor structure formed at the front side of the first substrate, having a first conductive contact; a recess formed at the backside of the first substrate to expose at least a portion of the dielectric layer; and a second conductive layer above the exposed dielectric layer.

Abstract: Embodiments of methods for forming three-dimensional (3D) memory devices are disclosed. In an example, a peripheral device is formed on a first substrate. A first interconnect layer is formed above the peripheral device on the first substrate. A dielectric stack including a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack is formed on a second substrate. A second interconnect layer is formed above the memory strings on the second substrate. The first substrate and the second substrate are bonded, so that the first interconnect layer is below and in contact with the second interconnect layer. The second substrate is thinned after the bonding. A memory stack is formed below the thinned second substrate and including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact and the second bonding contact includes a capping layer at the bonding interface and having a conductive material different from a remainder of the respective first or second bonding contact.

Abstract: A lubrication system includes an engine oil pump, a lubricating oil tank, a breathing pipe, a machine body, and an oil pan. The engine oil pump is formed by superposing upper and lower layers being a lubricating pump and an oil return pump. An oil inlet of the oil return pump leads to a cavity of the oil pan, and an oil outlet leads to an interior of the lubricating oil tank. An oil inlet of the lubricating pump leads to the interior of the lubricating oil tank, and an oil outlet leads to a machine filter. The machine filter is communicated with a main oil path of the machine body. An oil tank cover of the lubricating oil tank is provided with a breathing one-way valve and an oil filling port. The breathing one-way valve communicates one end of the breathing pipe, and the other end thereof communicates a crankcase.

Abstract: Compositions containing one or more compounds with inhibitory effect on a 5-HT3a and/or NK-1 receptor are effective for preventing or treating idiopathic vomiting in a mammal.

Abstract: Provided is an application providing method of an electronic device, the application providing method including: obtaining manipulation information of a user with respect to an application provided by the electronic device; obtaining feeling information of the user; modifying a user interface of the application based on the manipulation information and the feeling information of the user; and providing the application including the modified user interface.

Abstract: Methods and systems are disclosed for boosting deep neural networks for deep learning. In one example, in a deep neural network including a first shallow network and a second shallow network, a first training sample is processed by the first shallow network using equal weights. A loss for the first shallow network is determined based on the processed training sample using equal weights. Weights for the second shallow network are adjusted based on the determined loss for the first shallow network. A second training sample is processed by the second shallow network using the adjusted weights. In another example, in a deep neural network including a first weak network and a second weak network, a first subset of training samples is processed by the first weak network using initialized weights. A classification error for the first weak network on the first subset of training samples is determined.

Abstract: Embodiments of methods for forming three-dimensional (3D) memory devices are disclosed. In an example, a peripheral device is formed on a first substrate. A first interconnect layer is formed above the peripheral device on the first substrate. A dielectric stack including a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack is formed on a second substrate. A second interconnect layer is formed above the memory strings on the second substrate. The first substrate and the second substrate are bonded, so that the first interconnect layer is below and in contact with the second interconnect layer. The second substrate is thinned after the bonding. A memory stack is formed below the thinned second substrate and including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs.

Abstract: Methods and systems are disclosed using improved training and learning for deep neural networks. In one example, a deep neural network includes a plurality of layers, and each layer has a plurality of nodes. For each L layer in the plurality of layers, the nodes of each L layer are randomly connected to nodes in a L+1 layer. For each L+1 layer in the plurality of layers, the nodes of each L+1 layer are connected to nodes in a subsequent L layer in a one-to-one manner. Parameters related to the nodes of each L layer are fixed. Parameters related to the nodes of each L+1 layers are updated, and L is an integer starting with 1. In another example, a deep neural network includes an input layer, output layer, and a plurality of hidden layers. Inputs for the input layer and labels for the output layer are determined related to a first sample. Similarity between different pairs of inputs and labels between a second sample with the first sample is estimated using Gaussian regression process.

Abstract: Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps.

Abstract: Described herein are hardware acceleration of random number generation for machine learning and deep learning applications. An apparatus (700) includes a uniform random number generator (URNG) circuit (710) to generate uniform random numbers and an adder circuit (750) that is coupled to the URNG circuit (710). The adder circuit hardware (750) accelerates generation of Gaussian random numbers for machine learning.

Abstract: Described herein are systems and methods for providing deeply stacked automated program synthesis. In one embodiment, an apparatus to perform automated program synthesis includes a memory to store instructions for automated program synthesis and a compute cluster coupled to the memory. The compute cluster supports the instructions for performing the automated program synthesis including partitioning sketched data into partitions, training diverse sets of individual program synthesis units each having different capabilities with partitioned sketched data and for each partition applying respective transformations, and generating sketched baseline data for each individual program synthesis unit.

Abstract: A CC-NBS-LRR gene NLR1-V encoded by the enduring and broad-spectrum gene Pm21 which is resistant to powdery mildew in the wheat-Haynaldiavillosa 6VS/6AL translocation line in Nannong 9918, and an expression vector and use thereof. The ORF sequence of the Gene NLR1-V having an NLR domain is as shown in SEQ ID NO: 1, and the encoded amino acid sequence is as shown in SEQ ID NO: 2.