Patents by Inventor Ping-Kun Wang

Ping-Kun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978336
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Cheng-Hui Tu, Chi-Ching Liu, Ting-Ying Shen, Yen-De Lee, Ping-Kun Wang
  • Publication number: 20210074356
    Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.
    Type: Application
    Filed: April 15, 2020
    Publication date: March 11, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Chang-Tsung Pai, Yu-Ting Chen, He-Hsuan Chao, Ming-Che Lin, Frederick Chen
  • Patent number: 10937495
    Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Norio Hattori, Chien-Min Wu, Chih-Hua Hung
  • Patent number: 10916307
    Abstract: A resistive memory apparatus and an operating method thereof are provided. In the method, a set operation having a first enhanced bias is performed on at least one memory cell in a resistive memory array of the resistive memory apparatus, in which the first enhanced bias is larger than a bias used in a normal execution of the set operation. A heat process is performed on the memory cell. A set operation having a second enhanced bias is performed on the memory cell, in which the second enhanced bias is larger than or equal to the first enhanced bias.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 9, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Shao-Ching Liao, Ping-Kun Wang
  • Publication number: 20210012839
    Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.
    Type: Application
    Filed: May 13, 2020
    Publication date: January 14, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
  • Publication number: 20210005255
    Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 7, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Norio Hattori, Chien-Min Wu, Chih-Hua Hung
  • Patent number: 10839899
    Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 17, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Shao-Ching Liao, Yu-Ting Chen, Ming-Che Lin, Chien-Min Wu, Chia-Hua Ho
  • Publication number: 20200350013
    Abstract: A resistive memory apparatus and an operating method thereof are provided. In the method, a set operation having a first enhanced bias is performed on at least one memory cell in a resistive memory array of the resistive memory apparatus, in which the first enhanced bias is larger than a bias used in a normal execution of the set operation. A heat process is performed on the memory cell. A set operation having a second enhanced bias is performed on the memory cell, in which the second enhanced bias is larger than or equal to the first enhanced bias.
    Type: Application
    Filed: December 23, 2019
    Publication date: November 5, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Shao-Ching Liao, Ping-Kun Wang
  • Patent number: 10770167
    Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 8, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Ming-Che Lin, Chien-Min Wu, He-Hsuan Chao, Chih-Cheng Fu, Shao-Ching Liao
  • Publication number: 20200265914
    Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 20, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Ming-Che Lin, Chien-Min Wu, He-Hsuan Chao, Chih-Cheng Fu, Shao-Ching Liao
  • Publication number: 20200235001
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
    Type: Application
    Filed: December 5, 2019
    Publication date: July 23, 2020
    Inventors: Cheng-Hui TU, Chi-Ching LIU, Ting-Ying SHEN, Yen-De LEE, Ping-Kun WANG
  • Patent number: 10714157
    Abstract: A non-volatile memory and a reset method thereof are provided. The reset method includes: performing a first reset operation on a plurality of memory cells; recording a plurality of first verifying currents respectively corresponding to a plurality of first failure memory cells; performing a second reset operation on the first failure memory cells, and verifying second failure memory cells to obtain a plurality of second verifying currents; setting a first voltage modify flag according to a plurality of first ratios between the first verifying currents and the respectively corresponding second verifying currents; and adjusting a reset voltage for performing the first reset operation and the second reset operation according to the first voltage modify flag.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: July 14, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Ngatik Cheung, Chia-Wen Cheng
  • Publication number: 20200165029
    Abstract: A metal lath having an integral hem structure includes a main body. The main body is formed by enclosing the metal lath so that the main body has a ring-shaped side wall. The side wall defines an accommodating space therein. Two ends of the main body are formed with openings to communicate with the accommodating space, respectively. One of the openings is integrally formed with a hem around an end edge of the opening by bending. The hem is integrally formed with the metal lath, which can reduce production time and cost effectively and can prevent the user from being cut by the metal lath.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Inventor: PING KUN WANG
  • Patent number: 10658036
    Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 19, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Shao-Ching Liao, Ping-Kun Wang, Ming-Che Lin, Min-Chih Wei, Chia-Hua Ho, Chien-Min Wu
  • Patent number: 10636842
    Abstract: A method for forming a resistive random access memory includes forming a layer stack, patterning the layer stack to form a plurality of stack structures, forming a protection layer along sidewalls of the plurality of stack structures, forming a first isolation structure between the plurality of stack structures, forming at least one recess in at least one stack structure to define a plurality of filament units, and forming a second isolation structure in the at least one recess. The layer stack includes a bottom electrode and a resistive switching layer on the bottom electrode.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 28, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chia-Wen Cheng, Yi-Hsiu Chen, Po-Yen Hsu, Ping-Kun Wang, Ming-Che Lin, He-Hsuan Chao
  • Patent number: 10636484
    Abstract: A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 28, 2020
    Assignee: Winbond Electronics Corporation
    Inventors: Frederick Chen, Ping-Kun Wang, Chih-Cheng Fu, Chien-Min Wu
  • Patent number: 10636486
    Abstract: A resistive memory including a first storage circuit, a verification circuit, a second storage circuit and a control circuit is provided. The first storage circuit includes various cell groups. Each of the cell groups includes at least one memory cell. The verification circuit is coupled to the first storage circuit to verify whether a specific operation performed on at least one of the memory cells was successful. The second storage circuit includes various flag bits. Each of the flag bits corresponds to a cell group. In a reset period, the control circuit is configured to perform a first reset operation or a second reset operation on a first memory cell of a specific cell group among the cell groups according to a specific flag bit corresponding to the specific cell group.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: April 28, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Ping-Kun Wang, Shao-Ching Liao, He-Hsuan Chao, Chen-Lung Huang, Chi-Ching Liu, Chien-Min Wu
  • Patent number: 10593877
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 17, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin, Chia-Hua Ho, Ming-Che Lin
  • Patent number: D878801
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: March 24, 2020
    Inventor: Ping Kun Wang
  • Patent number: D884300
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 12, 2020
    Inventor: Ping Kun Wang