Abstract: A shift register and driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register includes an input unit, a reset unit, a first control unit, a second control unit, a first output unit, a second output unit, a first signal output end and a second signal output end. Potential of the first signal output end is controlled by use of the input unit, the reset unit, the first control unit and the first output unit, and potential of the second signal output end is controlled by use of the input unit, the reset unit, the second control unit and the second output unit. The first control unit and the first output unit, the second control unit and the second output unit are utilized for controlling and sharing the input unit and the reset unit so that function of two shift register units are realized.

Abstract: The present disclosure provides a gate driving circuit comprising multiple stages of cascaded shift registers, each stage of shift register comprising an input subcircuit, a first reset subcircuit, a second reset subcircuit, an energy storage subcircuit, an output subcircuit and a pull-down node potential generation subcircuit, wherein at least two stages of shift registers share a pull-down node potential generation subcircuit. The present disclosure further provides a display panel comprising the gate driving circuit, and a method for driving the gate driving circuit.

Abstract: The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.

Abstract: A test circuit board adapted to be used on PCI-E slot is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.

Abstract: A test circuit board adapted to be used on USB connector is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.

Abstract: A test circuit board adapted to be used on memory slot is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.

Abstract: A test-used PCB having an in-series circuit involved with a join test action group (JTAG) signal is provided. A first JTAG connection interface and a second JTAG connection interface are configured on test circuit boards. Test circuit boards can be seriously connected with each other through the first JTAG connection interface and the second JTAG connection interface. Therefore, the efficiency of providing series test circuit boards, reducing TAP controller and JTAG port may be achieved.

Abstract: A test circuit board adapted to be used on SATA connector is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.

Abstract: Embodiments of the present invention disclose a SON-based terminal selection method related to the field of communications technologies, where a target terminal is selected pertinently to participate in implementation of a SON algorithm. The method provided by the embodiments of the present invention includes: determining a terminal selection criterion under a requirement of implementing different SON algorithms; and performing target terminal selection from managed terminals according to the terminal selection criterion. A system and a network entity corresponding to the method are also provided. By applying the technical solutions provided by the embodiments of the present invention, a target terminal can be selected pertinently to participate in implementation of the SON algorithm, which avoids waste of resources of terminals that do not need to participate in implementation of the SON algorithm, and improves user experience of these terminals.

Abstract: A device and a system for processing a radio link failure report and for statistically processing an abnormal event include: a user equipment generates a radio link failure report, wherein the radio link failure report carries an A2 event indication recorded by the user equipment; and reports the radio link failure report.

Abstract: A thin film transistor and its manufacturing method are provided. The thin film transistor comprises an active layer on a substrate, and further comprises an ultraviolet light blocking layer positioned on a side of the active layer away from the substrate, and the active layer has a projection on the substrate which is within a projection of the ultraviolet light blocking layer on the substrate. The active layer is completely covered by the ultraviolet light blocking layer, and during the photo-alignment process, the ultraviolet light blocking layer can effectively eliminate the influence of the ultraviolet light on the active layer of the thin film transistor and ensure that the performance of the thin film transistor will not be affected by irradiation of the ultraviolet light.

Abstract: A user assigns a major and minor channel number combination to a media service which does not have such a pre-existing combination, where such a media service is accessed by using such a channel combination without having to resort to the typical means of accessing the media service, such as using a web site URL or radio frequency. Optionally, the invention will automatically update the minor numbers associated with a media service when older versions of the media service become unavailable.

Abstract: The present invention relates to the field of display technology, and discloses an array substrate, a manufacturing method thereof and a display device, for reducing the light leakage of a display device. The array substrate comprises a plurality of pixel regions arranged in arrays on a base substrate, two adjacent ones of the pixel regions having a signal line arranged therebetween, and the pixel regions and the signal line having a gap therebetween, wherein the array substrate further comprises at least one light-leakage-proof electrode arranged to be insulated from the pixel regions and the signal line, and the vertical projection of the light-leakage-proof electrode on the base substrate at least covers a portion of the vertical projection of the gap on the base substrate. The present invention is applicable in the field of display technology.

Abstract: Embodiments of the present invention relate to a method for determining a scrambling code conflict and an apparatus for determining a scrambling code conflict. The method includes: determining a serving cell before a handover of a user equipment fails, and determining a current serving cell of the user equipment; and comparing frequencies and scrambling codes of the current serving cell and a neighboring cell of the serving cell before the handover fails, and determining, according to a result of the comparing, that a scrambling code conflict exists between the current serving cell and the neighboring cell of the serving cell before the handover fails. A probability of a handover failure of a user equipment is reduced, so as to ensure that a service of the user equipment runs normally.

Abstract: The present invention provides a display panel and a display device. The display panel comprises an array substrate and a color filter substrate assembled in an aligned manner, the array substrate comprises a display area and a lead wire area provided on the periphery of at least one side of the display area, a first boundary line of the color filter substrate close to one side of the lead wire area has an orthographic projection on the array substrate and the orthographic projection falls into a boundary area of the lead wire area adjacent to the display area, a protective layer is provided on one side of the boundary area facing the color filter substrate, and the protective layer covers parts of the boundary area corresponding to the orthographic projection of the first boundary line on the array substrate and lead wires surrounding the parts.

Abstract: Techniques are described herein that are capable of generating a graphic flow having an unlimited number of connections between shapes. The shapes are provided in a visual representation of a workspace defined by pixels. For instance, a first shape may have an outer perimeter defined by a first subset of the pixels; a second shape may have an outer boundary defined by a second subset of the pixels, and so on. Any pixel in each subset may serve as a connection point. For example, a first pixel of the first subset may serve as a first connection point based on any of a variety of first criteria, and a second pixel of the second subset may serve as a second connection point based on any of a variety of second criteria. In accordance with this example, a connection may be provided between the first and second connection points.

Abstract: The present invention provides a display panel and a display device. The display panel comprises an array substrate and a color filter substrate assembled in an aligned manner, the array substrate comprises a display area and a lead wire area provided on the periphery of at least one side of the display area, a first boundary line of the color filter substrate close to one side of the lead wire area has an orthographic projection on the array substrate and the orthographic projection falls into a boundary area of the lead wire area adjacent to the display area, a protective layer is provided on one side of the boundary area facing the color filter substrate, and the protective layer covers parts of the boundary area corresponding to the orthographic projection of the first boundary line on the array substrate and lead wires surrounding the parts.

Abstract: This disclosure relates to an array substrate and fabricating method thereof as well as a display device, the array substrate comprising: a plurality of scanning lines and a plurality of signal lines, the plurality of scanning lines and plurality of signal lines defining a plurality of pixel regions; and a shielding electrode line arranged above the signal line between adjacent pixel regions, for shielding signal interference between pixel electrodes in the adjacent pixel regions. By means of the technical solution of this disclosure, the shielding electrode line arranged between adjacent pixels can shield crosstalk between the pixel electrodes of adjacent pixels, and can form a transverse storage capacitance with the pixel electrode in the pixel, thereby increasing the total storage capacitance, and maintaining voltage difference between the pixel electrode and a common electrode, so as to diminish the influence of the leakage current and prevent image flicker effectively.

Abstract: The present disclosure provides a shift register, comprising: a first input module, a second input module, an energy storage module, an output module and a reset module; and two shift signal input terminals, a reset control signal input terminal, a second electrical level input terminal and a first electrical level input terminal; a control terminal and an input terminal of the first input module being connected with the first shift signal input terminal, a control terminal and an input terminal of the second input module being connected with the second shift signal input terminal; output terminals of the first input module and the second input module as well as a first terminal of the energy storage module all being connected with a first node; the first input module and the second input module being configured to be turned on when the first or second shift signal input terminal accesses a first electrical level, and set the voltage of the first node to the first electrical level.

Abstract: Techniques are described herein that are capable of generating a graphic flow having an unlimited number of connections between shapes. The shapes are provided in a visual representation of a workspace defined by pixels. For instance, a first shape may have an outer perimeter defined by a first subset of the pixels; a second shape may have an outer boundary defined by a second subset of the pixels, and so on. Any pixel in each subset may serve as a connection point. For example, a first pixel of the first subset may serve as a first connection point based on any of a variety of first criteria, and a second pixel of the second subset may serve as a second connection point based on any of a variety of second criteria. In accordance with this example, a connection may be provided between the first and second connection points.