Abstract: A memory device may comprise a memory cell including first, second, third, fourth, fifth, sixth, and seventh transistors. The first to third transistors can be operatively formed from a first active region extending along a first lateral direction and each may have a respective gate structure extending along a second lateral direction. The fourth to seventh transistors can be operatively formed from a second active region extending along the first lateral direction and each may have a respective gate structure extending along the second lateral direction. The gate structures of the first to third transistors each may have a first measurement extending in the first lateral direction. The gate structures of the fourth to seventh transistors each may have a second measurement extending in the first lateral direction. The first measurement can be shorter than the second measurement.

Abstract: A semiconductor structure includes a first source/drain (S/D) epitaxial feature, a second S/D epitaxial feature adjacent to the first S/D epitaxial feature, an insulating structure between the first and the second S/D epitaxial features, and a shared S/D contact over top surfaces of the first and the second S/D epitaxial features. A center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature. The center portion is directly above the insulating structure. The semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.

Abstract: Semiconductor structures and methods of the forming the same are provided. A semiconductor structure includes a source feature and a drain feature, an active region between the source feature and the drain feature, a gate structure over the active region, a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure, a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure, and a storage element disposed in the backside interconnect structure.

Abstract: A semiconductor structure according to the present disclosure includes a first active region and a second active region, a first gate structure disposed over the first active region, a second gate structure disposed over the second active region, and a gate isolation feature sandwiched between a sidewall of the first gate structure and a sidewall of the second gate structure. The gate isolation feature includes a first dielectric layer interfacing the sidewall of the first gate structure and the sidewall of the second gate structure, a diffusion barrier liner interfacing the first dielectric layer, and a second dielectric layer interfacing the diffusion barrier liner. The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier liner.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

Abstract: A memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. Each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source/drain feature and a second source/drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source/drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source/drain feature.

Abstract: A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

Abstract: An integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs), a front metal line over the FETs and a back metal line below the FETs, and a middle strap area disposed between the first SRAM cell and the second SRAM cell. The middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first SRAM cell, and a second dielectric gate disposed between the conductive structure and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

Abstract: A method according to the present disclosure includes forming, over a substrate, a semiconductor stack that includes first semiconductor layers interleaved by second semiconductor layers, patterning the semiconductor stack and the substrate to form a fin-shaped structure, forming a dummy gate stack over the fin-shaped structure, recessing the fin-shaped structure to form a source/drain recess, selectively recessing the plurality of second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, depositing a first epitaxial layer over the source/drain recess, depositing a second epitaxial layer over the first epitaxial layer, depositing a buffer layer over the second epitaxial layer, depositing a third epitaxial layer over the buffer layer, removing the dummy gate stack, selectively removing the second semiconductor layers to release the first semiconductor layers as channel members, and forming a gate structure to wrap around each of the channel members.

Abstract: A memory cell includes an active region extending lengthwise along a first direction and first and second gate structures extending lengthwise along a second direction different from the first direction. The first gate structure engages the active region in forming a first transistor, and the second gate structure engages the active region in forming a second transistor. The memory cell further includes a first epitaxial feature disposed on a source region of the first transistor, a second epitaxial feature disposed on a common drain region of the first and second transistors, a backside contact disposed under and in electrical coupling with the first epitaxial feature, a backside signal line disposed under and in electrical coupling with the backside contact, and a first frontside contact disposed above and in electrical coupling with the second epitaxial feature.

Abstract: A memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region having a third width. The third width is larger than the first width, and the first width is larger than the second width.

Abstract: Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. In some embodiments, an implantation process is performed to implant a dopant into a S/D region to improve device performance. For example, source/drain regions of the transistors in a SRAM cell may be enhanced by additional dopants to improve the SRAM cell performance.

Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; a SRAM circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each of the SRAM bit cells is connected to a WBL, a WBLB, a RBL, a Vdd and a Vss; a first subset of WBL, WBLB, RBL, Vdd and Vss is connected to a first SRAM bit cell of the SRAM bit cells from the frontside of the substrate; and a second subset of WBL, WBLB, RBL, Vdd and Vss is connected to the first SRAM bit cell from the backside of the substrate.

Abstract: Semiconductor structures and methods of fabricating the semiconductor structures are described. An exemplary method includes receiving an intermediate structure comprising an n-type transistor and a p-type transistor, forming a dielectric structure under the n-type transistor and the p-type transistor, forming a first trench and a second trench each extending through the dielectric structure, the first trench exposing a bottom surface of a source/drain feature of the n-type transistor, the second trench exposing a bottom surface of a source/drain feature of the p-type transistor, wherein a depth of the second trench is greater than a depth of the first trench, forming a first silicide layer and a second silicide layer in the first trench and the second trench, respectively, and forming a first backside via and a second backside via in the first trench and the second trench, respectively.

Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary method includes forming a fin over a substrate, a first portion of the fin comprising a plurality of first channel layers interleaved by a plurality of first sacrificial layers, and a second portion of the fin comprising a plurality of second channel layers interleaved by a plurality of second sacrificial layers, forming a trench extending through the fin, laterally recessing the plurality of first sacrificial layers and the plurality of second sacrificial layers at different etch rates, and replacing a remaining portion of the plurality of first sacrificial layers with a first gate structure and replacing a remaining portion of the plurality of second sacrificial layers with a second gate structure.

Abstract: A memory device includes a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on the first side of the substrate, the first to third transistors each formed with a first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, the fourth to seventh transistors each formed with a second conductivity, wherein the first level is vertically disposed with respect to the second level. The first to seventh transistors operatively form a Static Random Access Memory (SRAM) cell.