Abstract: An integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs), a front metal line over the FETs and a back metal line below the FETs, and a middle strap area disposed between the first SRAM cell and the second SRAM cell. The middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first SRAM cell, and a second dielectric gate disposed between the conductive structure and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

Abstract: A method according to the present disclosure includes forming, over a substrate, a semiconductor stack that includes first semiconductor layers interleaved by second semiconductor layers, patterning the semiconductor stack and the substrate to form a fin-shaped structure, forming a dummy gate stack over the fin-shaped structure, recessing the fin-shaped structure to form a source/drain recess, selectively recessing the plurality of second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, depositing a first epitaxial layer over the source/drain recess, depositing a second epitaxial layer over the first epitaxial layer, depositing a buffer layer over the second epitaxial layer, depositing a third epitaxial layer over the buffer layer, removing the dummy gate stack, selectively removing the second semiconductor layers to release the first semiconductor layers as channel members, and forming a gate structure to wrap around each of the channel members.

Abstract: A memory cell includes an active region extending lengthwise along a first direction and first and second gate structures extending lengthwise along a second direction different from the first direction. The first gate structure engages the active region in forming a first transistor, and the second gate structure engages the active region in forming a second transistor. The memory cell further includes a first epitaxial feature disposed on a source region of the first transistor, a second epitaxial feature disposed on a common drain region of the first and second transistors, a backside contact disposed under and in electrical coupling with the first epitaxial feature, a backside signal line disposed under and in electrical coupling with the backside contact, and a first frontside contact disposed above and in electrical coupling with the second epitaxial feature.

Abstract: A memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region having a third width. The third width is larger than the first width, and the first width is larger than the second width.

Abstract: Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. In some embodiments, an implantation process is performed to implant a dopant into a S/D region to improve device performance. For example, source/drain regions of the transistors in a SRAM cell may be enhanced by additional dopants to improve the SRAM cell performance.

Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; a SRAM circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each of the SRAM bit cells is connected to a WBL, a WBLB, a RBL, a Vdd and a Vss; a first subset of WBL, WBLB, RBL, Vdd and Vss is connected to a first SRAM bit cell of the SRAM bit cells from the frontside of the substrate; and a second subset of WBL, WBLB, RBL, Vdd and Vss is connected to the first SRAM bit cell from the backside of the substrate.

Abstract: Semiconductor structures and methods of fabricating the semiconductor structures are described. An exemplary method includes receiving an intermediate structure comprising an n-type transistor and a p-type transistor, forming a dielectric structure under the n-type transistor and the p-type transistor, forming a first trench and a second trench each extending through the dielectric structure, the first trench exposing a bottom surface of a source/drain feature of the n-type transistor, the second trench exposing a bottom surface of a source/drain feature of the p-type transistor, wherein a depth of the second trench is greater than a depth of the first trench, forming a first silicide layer and a second silicide layer in the first trench and the second trench, respectively, and forming a first backside via and a second backside via in the first trench and the second trench, respectively.

Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary method includes forming a fin over a substrate, a first portion of the fin comprising a plurality of first channel layers interleaved by a plurality of first sacrificial layers, and a second portion of the fin comprising a plurality of second channel layers interleaved by a plurality of second sacrificial layers, forming a trench extending through the fin, laterally recessing the plurality of first sacrificial layers and the plurality of second sacrificial layers at different etch rates, and replacing a remaining portion of the plurality of first sacrificial layers with a first gate structure and replacing a remaining portion of the plurality of second sacrificial layers with a second gate structure.

Abstract: A memory device includes a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on the first side of the substrate, the first to third transistors each formed with a first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, the fourth to seventh transistors each formed with a second conductivity, wherein the first level is vertically disposed with respect to the second level. The first to seventh transistors operatively form a Static Random Access Memory (SRAM) cell.

Abstract: A device includes a first, second, third, and fourth transistor and a first and second conductor. The first transistor is coupled to a first node and includes a first gate. The second transistor is coupled to the first node, the second transistor includes a second gate. The third transistor is coupled to a second node, and includes a third gate separated from the first gate in a first direction. The fourth transistor is coupled to the second node, and includes a fourth gate. The first conductor is on a first metal layer above a front-side of a substrate, and is coupled to the first gate and the second node. The second conductor is on a second metal layer below a back-side of the substrate, and is coupled to the fourth gate and the first node.

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Abstract: An IC device includes a static random-access memory (SRAM) device positioned in a substrate, the SRAM device including a first complementary field-effect transistor (CFET) including a first pass-gate transistor positioned at a first elevation, a second CFET including a first pull-down transistor positioned at the first elevation and a first pull-up transistor positioned at a second elevation, a third CFET including a second pull-down transistor positioned at the first elevation and a second pull-up transistor positioned at the second elevation, and a fourth CFET including a second pass-gate transistor positioned at the first elevation. Each of the first and second pull-down transistors includes a gate extending in a gate direction and including a first work function configuration, and each of the first and second pass-gate transistors includes a gate extending in the gate direction and including a second work function configuration different from the first work function configuration.

Abstract: The present disclosure provides an IC structure that includes a substrate having a SRAM region, a logic region, and an edge region spanning between the SRAM region and the logic region; doped wells formed in the substrate and including a first N-well, a second N-well and a P-well; active regions formed on the doped wells and longitudinally oriented along a first direction; a STI structure formed on the substrate and surrounding the active regions; gate structures formed on the active regions and longitudinally oriented along a second direction perpendicular to the first direction; and a first isolation structure formed in the edge region and longitudinally oriented along the second direction, wherein the gate structures and the first isolation structure are evenly distributed along the first direction with a periodic dimension Pg, the first and second N-wells are distanced by a first dimension less than 3*Pg and separated by the P-well.

Abstract: Semiconductor devices and methods are provided. An exemplary method includes forming a first fin and a second fin, each of the first fin and the second fin comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, forming a first gate stack and a second gate stack over the first fin and the second fin, respectively, the first gate stack and the second gate stack having different gate lengths, forming a first source/drain feature adjacent to the first gate stack and a second source/drain feature adjacent to the second gate stack, after forming the second source/drain feature, performing an ion implantation process to increase a dopant concentration of an upper portion of the second source/drain feature.

Abstract: An integrated circuit device includes a pair of stacked active-region structures extending in a first direction. The integrated circuit also includes a first switching gate-conductor, a first CFET gate-conductor, a second CFET gate-conductor, and a second switching gate-conductor intersecting the pair of stacked active-region structures and aligned correspondingly with a first gate track, a second gate track, a third gate track, and a fourth gate track extending in a second direction. A first CFET terminal-conductor extending in the second direction between the first gate track and the second gate track is conductively connected to the second CFET gate-conductor. A second CFET terminal-conductor extending in the second direction between the third gate track and the fourth gate track is conductively connected to the first CFET gate-conductor.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: An IC device includes CFETs configured as a SRAM, a first CFET includes first pull-down and pull-up transistors at first and second elevations along a first direction, second and third CFETs includes pass gates at the first elevation and aligned with the first pull-down transistor in second and third directions perpendicular to the first direction, and a fourth CFET includes second pull-down and pull-up transistors at the first and second elevations and aligned with the pass gates in the second and third directions. First and second bit lines extend in the third direction at a third elevation and are electrically connected to S/D structures of the pass gates, and a reference voltage line extends between the bit lines at the third elevation and is electrically connected to a S/D structure of a pull-down transistor.

Abstract: A device includes a substrate having a first side and a second side; a first transistor and a second transistor formed in a first level on the first side; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor formed in a second level on the first side; a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side, the first and second interconnect structures each configured to carry a supply voltage, and the third and fourth interconnect structures each configured to carry a ground voltage; and a power structure vertically extending through the first and second levels, and configured to electrically couple a source/drain terminal of the third transistor and a source/drain terminal of the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively.

Abstract: Semiconductor structures and methods of the forming the same are provided. A semiconductor structure includes a source feature and a drain feature, an active region between the source feature and the drain feature, a gate structure over the active region, a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure, a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure, and a storage element disposed in the backside interconnect structure.

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.