Patents by Inventor Ping-Wei Wang

Ping-Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240292592
    Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
  • Publication number: 20240292590
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 29, 2024
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 12057505
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first well region and a second well region and a first fin structure formed in a first region of the first well region. The semiconductor device structure also includes a second fin structure formed in a second region of the first well region. In addition, the second fin structure is narrower than the first fin structure. The semiconductor device structure also includes a third fin structure formed in a first region of the second well region. In addition, a sidewall of the first fin structure is substantially aligned with a sidewall of the third fin structure.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 12046276
    Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chuan Yang, Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang
  • Patent number: 12048135
    Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Feng-Ming Chang, Kian-Long Lim, Ping-Wei Wang, Lien Jung Hung, Ruey-Wen Chang
  • Publication number: 20240237323
    Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary semiconductor device includes a circuit region, a first WPU region, second WPU region, a first well of a first conductivity type, and a second well of a second conductivity type. The circuit region, the first WPU region, and the second WPU region are arranged along a first direction in sequence. The first well has a first portion disposed in the circuit region and a second portion disposed in the first WPU region. The second well has a first portion disposed in the circuit region, a second portion disposed in the first WPU region, and a third potion disposed in the second WPU region. Measured along the first direction a width of the first WPU region is less than a width of the second WPU region.
    Type: Application
    Filed: February 19, 2024
    Publication date: July 11, 2024
    Inventors: Chih-Chuan Yang, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 12027202
    Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Wei Wang, Chia-Hao Pao, Choh Fei Yeap, Yu-Kuan Lin, Kian-Long Lim
  • Publication number: 20240215230
    Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen SU, Yu-Kuan LIN, Shih-Hao LIN, Lien-Jung HUNG, Ping-Wei WANG
  • Patent number: 12022664
    Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Lin Chen, Chenchen Jacob Wang, Hsin-Wen Su, Ping-Wei Wang, Yuan-Hao Chang, Po-Sheng Lu, Shih-Hao Lin
  • Publication number: 20240203486
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Application
    Filed: January 22, 2024
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan YANG, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 12016169
    Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin, Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Choh Fei Yeap
  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240153949
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • Patent number: 11980016
    Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
  • Patent number: 11968817
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11961769
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11956948
    Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Yu-Kuan Lin, Shih-Hao Lin, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 11942145
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20240098960
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
  • Publication number: 20240064950
    Abstract: A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Inventors: Jui-Lin Chen, Kian-Long Lim, Feng-Ming Chang, Yi-Feng Ting, Hsin-Wen Su, Lien-Jung Hung, Ping-Wei Wang