Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure and a second fin structure over the substrate. A top surface of the first fin structure and a top surface of the second fin structure are at different height levels. The semiconductor device structure also includes a first semiconductor element on the first fin structure and a second semiconductor element on the second fin structure. The first semiconductor element is wider than the second semiconductor element, and the first semiconductor element is closer to the substrate than the second semiconductor element.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively.

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

Abstract: A memory device includes a substrate, an active region, a first gate structure, a second gate structure, a first word line, and a second word line. The active region protrudes from a top surface of the substrate. The active region has at least one ring structure, in which when viewed from above, the ring structure has a first linear portion, a second linear portion, a first curved portion, and a second curved portion, the first curved portion connects first sides of the first and second linear portions, and the second curved portion connects second sides of the first and second linear portions. The first gate structure and the second gate structure are over the substrate and cross the active region. The first word line and the second word line are electrically connected to the first gate structure and the second gate structure, respectively.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first fin structure, a second fin structure, and a third fin structure over the semiconductor substrate. The semiconductor device structure also includes a merged semiconductor element on the first fin structure and the second fin structure and an isolated semiconductor element on the third fin structure. The semiconductor device structure further includes an isolation feature over the semiconductor substrate and partially or completely surrounding the first fin structure, the second fin structure, and the third fin structure. A top surface of the first fin structure is below a top surface of the isolation feature, and a top surface of the third fin structure is above the top surface of the isolation feature.

Abstract: A method includes forming a first fin protruding from a substrate in a first region of the substrate and a second fin protruding from the substrate in a second region of the substrate, recessing a portion of the first fin, thereby forming a first recess, recessing a portion of the second fin, thereby forming a second recess, depositing a blocking layer in the second recess, growing a base epitaxial layer in the first recess, removing the blocking layer from the second recess, and growing a doped epitaxial layer in the first recess and the second recess. The base epitaxial layer is dopant free. The doped epitaxial layer abuts the first fin in the first region and the second fin in the second region.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming a first gate structure over the substrate and crossing the first semiconductor fin; forming a second gate structure over the substrate and crossing the second semiconductor fin; forming a first gate spacer on a sidewall of the first gate structure; and forming a second gate spacer on a sidewall of the second gate structure, wherein in a top view, an outer sidewall of the first gate spacer farthest from the first gate structure is coterminous with an outer sidewall of the second gate spacer farthest from the second gate structure, and an inner sidewall of the first gate spacer in contact with the first gate structure is misaligned with an inner sidewall of the second gate spacer in contact with the second gate structure.

Abstract: A method according to the present disclosure includes forming a fin-shaped structure protruding from a substrate, forming a gate structure intersecting the fin-shaped structure, forming a gate spacer on a sidewall of the gate structure, and forming a conductive feature above the fin-shaped structure. The gate spacer is laterally between the gate structure and the conductive feature. The method also includes depositing a dielectric layer over the gate structure and the conductive feature, performing an etching process, thereby forming an opening through the dielectric layer and exposing top surfaces of the conductive feature and the gate structure, recessing the gate spacers through the opening, thereby exposing the sidewall of the gate structure, and forming a contact feature in the opening, wherein the contact feature is in contact with the conductive feature and has a bottom portion protruding downward to be in contact with the sidewall of the gate structure.

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

Abstract: A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first, second, and fifth gates are electrically connected, and wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected.

Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively.

Abstract: A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.

Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: A static random access memory (SRAM) includes a bit cell including a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a read multiplexer connected to the bit information path. The read multiplexer includes an n-type transistor configured to selectively couple the bit information path to a sense amplifier.

Abstract: Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.