Patents by Inventor Piotr Wysocki

Piotr Wysocki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971782
    Abstract: Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 30, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20230297271
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 21, 2023
    Inventors: Michal Wysoczanski, Kapil Karkra, Piotr Wysocki, Anand S. Ramalingam
  • Patent number: 11709623
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: July 25, 2023
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Michal Wysoczanski, Kapil Karkra, Piotr Wysocki, Anand S. Ramalingam
  • Patent number: 11687498
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Jawad B. Khan, Piotr Wysocki
  • Publication number: 20230105491
    Abstract: Examples described herein relate to a system to estimate latency of operations of a process without receiving a latency value directly based on received performance values and/or estimate throughput of packets transmitted for the process without receiving a throughput value directly based on received performance values. In some examples, the system is to request to adjust resource allocation to perform the process based on the determined latency and throughput.
    Type: Application
    Filed: December 2, 2022
    Publication date: April 6, 2023
    Inventors: Mrittika GANGULI, Dmytro YERMOLENKO, Adrian C. MOGA, Abhirupa LAYEK, Qiming LIU, Robert ZMUDA TRZEBIATOWSKI, Rafal SZNEJDER, Piotr WYSOCKI, Mohan J. KUMAR, Ranganath SUNKU, Vishakh NAIR
  • Publication number: 20230082403
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 20, 2020
    Publication date: March 16, 2023
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20220058062
    Abstract: Examples described herein relate to an including at least one processor and a system agent communicatively coupled to the at least one processor. In some examples, the at least one of the at least one processor, when operational, is configured to: execute an operating system (OS) to: receive a call to perform a kernel-level operation and adjust settings of system resources assigned to perform the kernel-level operation based on a class of service associated with the call.
    Type: Application
    Filed: November 7, 2021
    Publication date: February 24, 2022
    Inventors: Rafal SZTEJNA, Piotr WYSOCKI, Pawel ZAK, Przemyslaw PERYCZ, Szymon KONEFAL
  • Publication number: 20220027278
    Abstract: Examples include techniques for core-specific metrics collection. Examples include fetching metrics of a core of a multi-core processor from one or more registers responsive to scheduling of an event. The fetched metrics are pushed to a shared memory space of a memory that is accessible to a user-space application and accessible to other cores of the multi-core processor. The user-space application to access the shared memory space to aggregate core-specific metrics associated with at least the core of the multi-core processor and then publish the aggregated core-specific metrics.
    Type: Application
    Filed: October 6, 2021
    Publication date: January 27, 2022
    Inventors: Piotr WYSOCKI, Francesc GUIM BERNAT, John J. BROWNE, Pawel ZAK, Rafal SZTEJNA, Przemyslaw PERYCZ, Timothy VERRALL, Szymon KONEFAL
  • Patent number: 11137916
    Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Michael Mesnier, Kapil Karkra, Piotr Wysocki, Jonathan Hughes, Brennan Watt, Sanjeev Trika, Anand Ramalingam
  • Patent number: 11132215
    Abstract: Techniques to facilitate an out-of-band (OOB) management in a virtualization environment include examples of assigning an endpoint identifier to a domain mapped to physical memory addresses of one or more storage devices coupled with a computing platform. The domain may enable software or a device driver executed by a virtual machine (VM) to access, manage or control at least a portion of the one or more storage devices. Examples also include receiving or forwarding messages through an OOB communication link coupled with the computing platform to a management entity to facilitate OOB management of the software or the device driver executed by the VM.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Maksymilian Kunt, Piotr Wysocki, Slawomir Ptak, Kapil Karkra
  • Publication number: 20210279186
    Abstract: Dynamically controlled interrupt coalescing is performed by enabling interrupt coalescing when the queue depth of the submission queue is high and disabling interrupt coalescing when the queue depth of the submission queue is low to maintain a required quality of service for a solid state drive. The minimum number of completions in the completion queue to trigger an interrupt is modified based on the queue depth of the submission queue. The minimum number of completions is increased when there is an increase in the queue depth of the submission queue and decreased when there is a decrease in the queue depth of the submission queue.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 9, 2021
    Applicant: Intel Corporation
    Inventors: Maksymilian KUNT, Piotr WYSOCKI, Mariusz BARCZAK
  • Publication number: 20210263895
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Applicant: Intel Corporation
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN, Piotr WYSOCKI
  • Publication number: 20210255955
    Abstract: Systems, apparatuses and methods may provide for technology that detects, via a processor external to a solid state drive (SSD), internal information associated with the SSD, detects background operations with respect to the SSD based on the internal information, wherein the background operations include one or more of current operations or predicted operations, and adjusts a hierarchical data placement policy based on the background operations.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Inventors: Sanjeev Trika, Piotr Wysocki
  • Patent number: 11068175
    Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Marcin Pioch, Michael Mesnier, Anand Ramalingam, Benjamin Boyer, Kapil Karkra, Piotr Wysocki
  • Patent number: 11025745
    Abstract: Technologies for end-to-end quality of service for I/O operations include a compute device in an I/O path. The compute device receives from another of the compute devices in the I/O path, an I/O request packet. The I/O request packet includes one or more QoS deadline metadata. The QoS deadline metadata is indicative of latency information relating to a currently executing workload relative to a specified QoS. The compute device evaluates the QoS deadline metadata and assigns a priority to the I/O request packet as a function of the evaluated metadata.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Piotr Wysocki, Maciej Andrzej Koprowski, Grzegorz Jereczek
  • Patent number: 11010350
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: May 18, 2021
    Assignee: INTEL CORPORATION
    Inventors: Sanjeev N. Trika, Jawad B. Khan, Piotr Wysocki
  • Publication number: 20210109679
    Abstract: Systems, apparatuses and methods may provide for technology that samples machine learning (ML) data from a local memory in accordance with a specified configuration, wherein the ML data is associated with one or more tasks submitted by one or more processor cores. The technology may also estimate the complexity of the sampled ML data based on one or more thresholds and schedule the task(s) for execution by one or more accelerators based on the complexity and telemetry data associated with a link to the accelerator(s).
    Type: Application
    Filed: December 18, 2020
    Publication date: April 15, 2021
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Piotr Wysocki
  • Patent number: 10936201
    Abstract: An embodiment of a semiconductor apparatus for use with redundant storage may include technology to cache all data for a write request for at least two member persistent storage drives in a persistent cache with a write access latency at least as low as a lowest write access latency of the at least two member persistent storage drives, write the data for the write request to one member persistent storage drive of the at least two member persistent storage drives, and indicate that the write request is complete after the data for the write request is redundantly stored in the persistent cache and the one member persistent storage drive. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Pawel Baldysiak, Piotr Wysocki, Slawomir Ptak
  • Patent number: 10877691
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Mariusz Barczak, Dhruvil Shah, Kapil Karkra, Andrzej Jakowski, Piotr Wysocki
  • Publication number: 20200264800
    Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Piotr WYSOCKI, Sanjeev N. TRIKA, Gregory B. TUCKER, Jackson ELLIS, Jonathan M. HUGHES