Patents by Inventor Piotr Wysocki

Piotr Wysocki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12253945
    Abstract: Systems, apparatuses and methods may provide for technology that detects, via a processor external to a solid state drive (SSD), internal information associated with the SSD, detects background operations with respect to the SSD based on the internal information, wherein the background operations include one or more of current operations or predicted operations, and adjusts a hierarchical data placement policy based on the background operations.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: March 18, 2025
    Assignee: Intel Corporation
    Inventors: Sanjeev Trika, Piotr Wysocki
  • Publication number: 20250053335
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Michal Wysoczanski, Kapil Karkra, Piotr Wysocki, Anand S. Ramalingam
  • Patent number: 12204470
    Abstract: Dynamically controlled interrupt coalescing is performed by enabling interrupt coalescing when the queue depth of the submission queue is high and disabling interrupt coalescing when the queue depth of the submission queue is low to maintain a required quality of service for a solid state drive. The minimum number of completions in the completion queue to trigger an interrupt is modified based on the queue depth of the submission queue. The minimum number of completions is increased when there is an increase in the queue depth of the submission queue and decreased when there is a decrease in the queue depth of the submission queue.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 21, 2025
    Assignee: Intel Corporation
    Inventors: Maksymilian Kunt, Piotr Wysocki, Mariusz Barczak
  • Patent number: 12197776
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: January 14, 2025
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Michal Wysoczanski, Kapil Karkra, Piotr Wysocki, Anand S. Ramalingam
  • Patent number: 12177131
    Abstract: A computing node includes a NIC and processing circuitry configured to select a subset of computing resources from a set of available computing resources to initiate a parameter sweep associated with a parameter sweep request received. A plurality of settings is applied to each computing resource of the subset to generate a plurality of resource mappings during the parameter sweep. Each resource mapping of the plurality of resource mappings indicates at least one computing resource of the subset and a corresponding at least one setting of the plurality of settings. Telemetry information for the subset of computing resources is retrieved, the telemetry information is generated during the parameter sweep. A resource mapping of the plurality of resource mappings is selected based on a comparison of the telemetry information with an SLO. A reconfiguration of the available computing resources is performed based on the selected resource mapping.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij Arun Doshi, Karol Weber, Marek Piotrowski, Piotr Wysocki
  • Patent number: 12112055
    Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: October 8, 2024
    Assignee: INTEL CORPORATION
    Inventors: Piotr Wysocki, Sanjeev N. Trika, Gregory B. Tucker, Jackson Ellis, Jonathan M. Hughes
  • Publication number: 20240241792
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20240236017
    Abstract: A computing node includes a NIC and processing circuitry configured to select a subset of computing resources from a set of available computing resources to initiate a parameter sweep associated with a parameter sweep request received. A plurality of settings is applied to each computing resource of the subset to generate a plurality of resource mappings during the parameter sweep. Each resource mapping of the plurality of resource mappings indicates at least one computing resource of the subset and a corresponding at least one setting of the plurality of settings. Telemetry information for the subset of computing resources is retrieved, the telemetry information is generated during the parameter sweep. A resource mapping of the plurality of resource mappings is selected based on a comparison of the telemetry information with an SLO. A reconfiguration of the available computing resources is performed based on the selected resource mapping.
    Type: Application
    Filed: June 25, 2021
    Publication date: July 11, 2024
    Inventors: Francesc Guim Bernat, Kshitij Arun Doshi, Karol Weber, Marek PIOTROWSKI, Piotr Wysocki
  • Patent number: 11971782
    Abstract: Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 30, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20230297271
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 21, 2023
    Inventors: Michal Wysoczanski, Kapil Karkra, Piotr Wysocki, Anand S. Ramalingam
  • Patent number: 11709623
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: July 25, 2023
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Michal Wysoczanski, Kapil Karkra, Piotr Wysocki, Anand S. Ramalingam
  • Patent number: 11687498
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Jawad B. Khan, Piotr Wysocki
  • Publication number: 20230105491
    Abstract: Examples described herein relate to a system to estimate latency of operations of a process without receiving a latency value directly based on received performance values and/or estimate throughput of packets transmitted for the process without receiving a throughput value directly based on received performance values. In some examples, the system is to request to adjust resource allocation to perform the process based on the determined latency and throughput.
    Type: Application
    Filed: December 2, 2022
    Publication date: April 6, 2023
    Inventors: Mrittika GANGULI, Dmytro YERMOLENKO, Adrian C. MOGA, Abhirupa LAYEK, Qiming LIU, Robert ZMUDA TRZEBIATOWSKI, Rafal SZNEJDER, Piotr WYSOCKI, Mohan J. KUMAR, Ranganath SUNKU, Vishakh NAIR
  • Publication number: 20230082403
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 20, 2020
    Publication date: March 16, 2023
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20220058062
    Abstract: Examples described herein relate to an including at least one processor and a system agent communicatively coupled to the at least one processor. In some examples, the at least one of the at least one processor, when operational, is configured to: execute an operating system (OS) to: receive a call to perform a kernel-level operation and adjust settings of system resources assigned to perform the kernel-level operation based on a class of service associated with the call.
    Type: Application
    Filed: November 7, 2021
    Publication date: February 24, 2022
    Inventors: Rafal SZTEJNA, Piotr WYSOCKI, Pawel ZAK, Przemyslaw PERYCZ, Szymon KONEFAL
  • Publication number: 20220027278
    Abstract: Examples include techniques for core-specific metrics collection. Examples include fetching metrics of a core of a multi-core processor from one or more registers responsive to scheduling of an event. The fetched metrics are pushed to a shared memory space of a memory that is accessible to a user-space application and accessible to other cores of the multi-core processor. The user-space application to access the shared memory space to aggregate core-specific metrics associated with at least the core of the multi-core processor and then publish the aggregated core-specific metrics.
    Type: Application
    Filed: October 6, 2021
    Publication date: January 27, 2022
    Inventors: Piotr WYSOCKI, Francesc GUIM BERNAT, John J. BROWNE, Pawel ZAK, Rafal SZTEJNA, Przemyslaw PERYCZ, Timothy VERRALL, Szymon KONEFAL
  • Patent number: 11137916
    Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Michael Mesnier, Kapil Karkra, Piotr Wysocki, Jonathan Hughes, Brennan Watt, Sanjeev Trika, Anand Ramalingam
  • Patent number: 11132215
    Abstract: Techniques to facilitate an out-of-band (OOB) management in a virtualization environment include examples of assigning an endpoint identifier to a domain mapped to physical memory addresses of one or more storage devices coupled with a computing platform. The domain may enable software or a device driver executed by a virtual machine (VM) to access, manage or control at least a portion of the one or more storage devices. Examples also include receiving or forwarding messages through an OOB communication link coupled with the computing platform to a management entity to facilitate OOB management of the software or the device driver executed by the VM.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Maksymilian Kunt, Piotr Wysocki, Slawomir Ptak, Kapil Karkra
  • Publication number: 20210279186
    Abstract: Dynamically controlled interrupt coalescing is performed by enabling interrupt coalescing when the queue depth of the submission queue is high and disabling interrupt coalescing when the queue depth of the submission queue is low to maintain a required quality of service for a solid state drive. The minimum number of completions in the completion queue to trigger an interrupt is modified based on the queue depth of the submission queue. The minimum number of completions is increased when there is an increase in the queue depth of the submission queue and decreased when there is a decrease in the queue depth of the submission queue.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 9, 2021
    Applicant: Intel Corporation
    Inventors: Maksymilian KUNT, Piotr WYSOCKI, Mariusz BARCZAK
  • Publication number: 20210263895
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Applicant: Intel Corporation
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN, Piotr WYSOCKI