Patents by Inventor Piotr Wysocki

Piotr Wysocki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190050161
    Abstract: Embodiments of the present disclosure may relate to a data storage apparatus that may include a redundancy logic to determine recovery data based on data in a storage region buffer; and a storage region controller to schedule a first set of non-volatile memory (NVM) dies in a first solid state drive (SSD) to be in a non-deterministic (ND) state or a deterministic (D) state, schedule a second set of NVM dies in a second SSD to be in a ND state or a D state, issue a first write command to write the data to the first set of NVM dies when the first set of NVM dies are in the ND state, and issue a second write command to write the recovery data to the second of NVM dies when the second set of NVM dies are in the ND state. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 21, 2018
    Publication date: February 14, 2019
    Inventors: Piotr Wysocki, Slawomir Ptak, Kapil Karkra, Marcin Pioch
  • Publication number: 20190042413
    Abstract: A host based Input/Output (I/O) scheduling system that improves read latency by reducing I/O collisions and improving I/O determinism of storage devices is provided. The host based storage region I/O scheduling system provides a predictable read latency using a combination of data redundancy, a host based scheduler and a write-back cache.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 7, 2019
    Inventors: Piotr WYSOCKI, Slawomir PTAK, Kapil KARKRA
  • Publication number: 20190045028
    Abstract: Technologies for end-to-end quality of service for I/O operations include a compute device in an I/O path. The compute device receives from another of the compute devices in the I/O path, an I/O request packet. The I/O request packet includes one or more QoS deadline metadata. The QoS deadline metadata is indicative of latency information relating to a currently executing workload relative to a specified QoS. The compute device evaluates the QoS deadline metadata and assigns a priority to the I/O request packet as a function of the evaluated metadata.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Inventors: Piotr Wysocki, Maciej Andrzej Koprowski, Grzegorz Jereczek
  • Publication number: 20190042114
    Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Inventors: Michael Mesnier, Kapil Karkra, Piotr Wysocki, Jonathan Hughes, Brennan Watt, Sanjeev Trika, Anand Ramalingam
  • Publication number: 20190042137
    Abstract: Technology for a nonvolatile memory (NVM) device is described. The NVM device can include a NVM interface structurally configured to communicatively couple to each of a plurality of NVM subunits of a NVM. The NVM device can include a first NVM controller communicatively coupleable to each of the plurality of NVM subunits through the NVM interface. The NVM device can include a second NVM controller communicatively coupleable to each of the plurality of NVM subunits through the NVM interface. The NVM device can include a demarcation divider dynamically positionable along the NVM interface to discretely partition the NVM interface between the first NVM controller and the second NVM controller.
    Type: Application
    Filed: February 5, 2018
    Publication date: February 7, 2019
    Inventor: Piotr Wysocki
  • Publication number: 20190042355
    Abstract: An apparatus may include a storage driver, the storage driver coupled to a processor, to a non-volatile random access memory (NVRAM), and to a redundant array of independent disks (RAID), the storage driver to: receive a memory write request from the processor for data stored in the NVRAM; calculate parity data from the data and store the parity data in the NVRAM; and write the data and the parity data to the RAID without prior storage of the data and the parity data to a journaling drive. In embodiments, the storage driver may be integrated with the RAID. In embodiments, the storage driver may write the data and the parity data to the RAID by direct memory access (DMA) of the NVRAM.
    Type: Application
    Filed: June 26, 2018
    Publication date: February 7, 2019
    Inventors: Slawomir Ptak, Piotr Wysocki, Kapil Karkra, Sanjeev N. Trika
  • Publication number: 20190042146
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 7, 2019
    Inventors: Michal WYSOCZANSKI, Kapil KARKRA, Piotr WYSOCKI, Anand S. RAMALINGAM
  • Publication number: 20190044857
    Abstract: Examples may include an apparatus having a packet receiver to receive a packet, the packet including a packet header having a deadline and a destination network node. The apparatus includes a routing table including a current latency for a path to the destination network node for the packet. The apparatus further includes a reprioritization component to get the deadline for delivery of the packet to the destination network node, to set a remaining time for the packet to the deadline minus a current time, to subtract the current latency from the remaining time when the packet is to be routed, and to assign the packet to one of a plurality of deadline bins based at least in part on the remaining time, each deadline bin associated with one of a plurality of transmit queues, the plurality of deadline bins arranged in a deadline priority order from a highest priority to a lowest priority.
    Type: Application
    Filed: July 27, 2018
    Publication date: February 7, 2019
    Inventors: Grzegorz JERECZEK, Maciej Andrzej KOPROWSKI, Piotr WYSOCKI
  • Publication number: 20190042594
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.
    Type: Application
    Filed: June 6, 2018
    Publication date: February 7, 2019
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN, Piotr WYSOCKI
  • Publication number: 20190034120
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: January 31, 2019
    Inventors: Mariusz Barczak, Dhruvil Shah, Kapil Karkra, Andrzej Jakowski, Piotr Wysocki
  • Publication number: 20190034306
    Abstract: Examples relate to a computer system, a computer system host, a first storage device, a second storage device, controllers, methods, apparatuses and computer programs. The computer system includes a first storage device and a second storage device. A storage region is distributed across the first storage device and the second storage device. The computer system further includes a computer system host. The computer system further includes a communication infrastructure configured to connect the first storage device, the second storage device and the computer system host. The computer system host is configured to transmit a request related to the storage region to the first storage device via the communication infrastructure. The first storage device is configured to issue a further request to the second storage device via the communication infrastructure to execute the request.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: Piotr Wysocki, Slawomir Ptak, Niels Reimers
  • Patent number: 10146688
    Abstract: An embodiment of a cache apparatus may include a first cache memory, a second cache memory, and a cache controller communicatively coupled to the first cache memory and the second cache memory to allocate cache storage for clean data from one of either the first cache memory or the second cache memory, and allocate cache storage for dirty data from both the first cache memory and the second cache memory. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Maciej Kaminski, Andrzej Jakowski, Piotr Wysocki
  • Publication number: 20180285275
    Abstract: Provided are an apparatus, computer program product, and method to perform cache operations in a solid state drive. A cache memory determines whether data for a requested storage address in a primary storage namespace received from a host system is stored at an address in the cache memory namespace to which the requested storage address maps according to a cache mapping scheme. Multiple of the storage addresses in the primary storage map to one address in the cache memory namespace. The cache memory returns to the host system the data at the requested address stored in the cache memory namespace in response to determining that the data for the requested storage address is stored in the cache memory namespace.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Mariusz BARCZAK, Piotr WYSOCKI
  • Publication number: 20180189178
    Abstract: An embodiment of a cache apparatus may include a first cache memory, a second cache memory, and a cache controller communicatively coupled to the first cache memory and the second cache memory to allocate cache storage for clean data from one of either the first cache memory or the second cache memory, and allocate cache storage for dirty data from both the first cache memory and the second cache memory. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Maciej Kaminski, Andrzej Jakowski, Piotr Wysocki
  • Publication number: 20180188985
    Abstract: An embodiment of a storage apparatus may include persistent storage media, a namespace having backend storage, and a virtual function controller communicatively coupled to the persistent storage media and the namespace to assign the namespace to a virtual storage function and to control access to the namespace by the virtual storage function. The virtual function controller may be further configured to cache access to the namespace on the persistent storage media. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Piotr Wysocki, Mariusz Barczak
  • Publication number: 20180095679
    Abstract: An electronic processing system may include a device driver to provide redundant array of independent disks (RAID) functionality. The device driver may include a detector to detect whether operation as a RAID controller device is established. The device driver may also include a controller to establish operation of a device as the RAID controller device when no device has established operation as the RAID controller device. The device driver may further include a publisher to publish a block device before exposure as usable storage, wherein publication of the block device is to be understood only by the RAID controller device.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Piotr Wysocki, Lukasz Lasek
  • Publication number: 20180095884
    Abstract: An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region system memory.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Maciej KAMINSKI, Piotr WYSOCKI, Slawomir PTAK
  • Patent number: 9921914
    Abstract: An apparatus includes a plurality of drives configured as a redundant array of independent disks (RAID) and drive array controller logic to: calculate a first partial parity log (PPL) value for a first write operation that targets a first active stripe of the plurality of drives; store the first PPL value in a first pre-allocated portion of the plurality of drives that depends on a first number associated with the first active stripe; calculate a second PPL value for a second write operation that targets a second active stripe of the plurality of drives; and store the second PPL value in a second pre-allocated portion of the plurality of drives that depends on a second number associated with the second active stripe.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Slawomir Ptak, Sanjeev N Trika, Piotr Wysocki, Kapil Karkra, Rajib Ghosal
  • Publication number: 20180004690
    Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to define a caching and processing priority policy for one or more input/output (I/O) request class types. The memory controller can monitor one or more I/O contexts of one or more I/O requests. The memory controller can associate the one or more I/O contexts with one or more I/O class types using an I/O context association table. The memory controller can execute the one or more I/O requests according to the caching and processing priority policy of the one or more I/O class types. The apparatus can include an interface to the memory controller.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: Intel Corporation
    Inventors: Maciej Kaminski, Piotr Wysocki, Mariusz Barczak
  • Publication number: 20170123921
    Abstract: An apparatus includes a plurality of drives configured as a redundant array of independent disks (RAID) and drive array controller logic to: calculate a first partial parity log (PPL) value for a first write operation that targets a first active stripe of the plurality of drives; store the first PPL value in a first pre-allocated portion of the plurality of drives that depends on a first number associated with the first active stripe; calculate a second PPL value for a second write operation that targets a second active stripe of the plurality of drives; and store the second PPL value in a second pre-allocated portion of the plurality of drives that depends on a second number associated with the second active stripe.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 4, 2017
    Inventors: Slawomir Ptak, Sanjeev N. Trika, Piotr Wysocki, Kapil Karkra, Rajib Ghosal