Patents by Inventor Piotr Wysocki

Piotr Wysocki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10715437
    Abstract: Examples may include an apparatus having a packet receiver to receive a packet, the packet including a packet header having a deadline and a destination network node. The apparatus includes a routing table including a current latency for a path to the destination network node for the packet. The apparatus further includes a reprioritization component to get the deadline for delivery of the packet to the destination network node, to set a remaining time for the packet to the deadline minus a current time, to subtract the current latency from the remaining time when the packet is to be routed, and to assign the packet to one of a plurality of deadline bins based at least in part on the remaining time, each deadline bin associated with one of a plurality of transmit queues, the plurality of deadline bins arranged in a deadline priority order from a highest priority to a lowest priority.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Grzegorz Jereczek, Maciej Andrzej Koprowski, Piotr Wysocki
  • Publication number: 20200174977
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Application
    Filed: January 27, 2020
    Publication date: June 4, 2020
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN, Piotr WYSOCKI
  • Patent number: 10545925
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Jawad B. Khan, Piotr Wysocki
  • Patent number: 10481979
    Abstract: According to various aspects, a storage system is provided, the storage system including a multiplicity of storage devices, and one or more processors configured to store user data on the multiplicity of storage devices, the stored user data being distributed among the multiplicity of storage devices together with redundancy data and with log data; generate a classification associated with the redundancy data and the log data to provide classified redundancy data and classified log data, and write the classified redundancy data and the classified log data on the respective storage device of the multiplicity of storage devices according to the classification associated therewith.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Marcin Pioch, Kapil Karkra, Piotr Wysocki, Slawomir Ptak
  • Publication number: 20190317796
    Abstract: Techniques to facilitate an out-of-band (OOB) management in a virtualization environment include examples of assigning an endpoint identifier to a domain mapped to physical memory addresses of one or more storage devices coupled with a computing platform. The domain may enable software or a device driver executed by a virtual machine (VM) to access, manage or control at least a portion of the one or more storage devices. Examples also include receiving or forwarding messages through an OOB communication link coupled with the computing platform to a management entity to facilitate OOB management of the software or the device driver executed by the VM.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Maksymilian KUNT, Piotr WYSOCKI, Slawomir PTAK, Kapil KARKRA
  • Publication number: 20190187917
    Abstract: An embodiment of a semiconductor apparatus for use with redundant storage may include technology to cache all data for a write request for at least two member persistent storage drives in a persistent cache with a write access latency at least as low as a lowest write access latency of the at least two member persistent storage drives, write the data for the write request to one member persistent storage drive of the at least two member persistent storage drives, and indicate that the write request is complete after the data for the write request is redundantly stored in the persistent cache and the one member persistent storage drive. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 20, 2019
    Inventors: Pawel Baldysiak, Piotr Wysocki, Slawomir Ptak
  • Publication number: 20190179554
    Abstract: An embodiment of a semiconductor apparatus may include technology to receive a request for a firmware update of one or more member drives of a redundant storage volume that includes at least two member persistent storage drives, and maintain continued access to the redundant storage volume during the firmware update of the one or more member drives of the redundant storage volume. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 13, 2019
    Inventors: Marcin Pioch, Piotr Wysocki, Slawomir Ptak
  • Patent number: 10318450
    Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to define a caching and processing priority policy for one or more input/output (I/O) request class types. The memory controller can monitor one or more I/O contexts of one or more I/O requests. The memory controller can associate the one or more I/O contexts with one or more I/O class types using an I/O context association table. The memory controller can execute the one or more I/O requests according to the caching and processing priority policy of the one or more I/O class types. The apparatus can include an interface to the memory controller.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Maciej Kaminski, Piotr Wysocki, Mariusz Barczak
  • Publication number: 20190146698
    Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Marcin Pioch, Michael Mesnier, Anand Ramalingam, Benjamin Boyer, Kapil Karkra, Piotr Wysocki
  • Publication number: 20190095281
    Abstract: According to various aspects, a storage system is provided, the storage system including a multiplicity of storage devices, and one or more processors configured to store user data on the multiplicity of storage devices, the stored user data being distributed among the multiplicity of storage devices together with redundancy data and with log data; generate a classification associated with the redundancy data and the log data to provide classified redundancy data and classified log data, and write the classified redundancy data and the classified log data on the respective storage device of the multiplicity of storage devices according to the classification associated therewith.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Marcin Pioch, Kapil Karkra, Piotr Wysocki, Slawomir Ptak
  • Patent number: 10228874
    Abstract: An embodiment of a storage apparatus may include persistent storage media, a namespace having backend storage, and a virtual function controller communicatively coupled to the persistent storage media and the namespace to assign the namespace to a virtual storage function and to control access to the namespace by the virtual storage function. The virtual function controller may be further configured to cache access to the namespace on the persistent storage media. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Piotr Wysocki, Mariusz Barczak
  • Patent number: 10223271
    Abstract: Provided are an apparatus, computer program product, and method to perform cache operations in a solid state drive. A cache memory determines whether data for a requested storage address in a primary storage namespace received from a host system is stored at an address in the cache memory namespace to which the requested storage address maps according to a cache mapping scheme. Multiple of the storage addresses in the primary storage map to one address in the cache memory namespace. The cache memory returns to the host system the data at the requested address stored in the cache memory namespace in response to determining that the data for the requested storage address is stored in the cache memory namespace.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mariusz Barczak, Piotr Wysocki
  • Publication number: 20190050161
    Abstract: Embodiments of the present disclosure may relate to a data storage apparatus that may include a redundancy logic to determine recovery data based on data in a storage region buffer; and a storage region controller to schedule a first set of non-volatile memory (NVM) dies in a first solid state drive (SSD) to be in a non-deterministic (ND) state or a deterministic (D) state, schedule a second set of NVM dies in a second SSD to be in a ND state or a D state, issue a first write command to write the data to the first set of NVM dies when the first set of NVM dies are in the ND state, and issue a second write command to write the recovery data to the second of NVM dies when the second set of NVM dies are in the ND state. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 21, 2018
    Publication date: February 14, 2019
    Inventors: Piotr Wysocki, Slawomir Ptak, Kapil Karkra, Marcin Pioch
  • Publication number: 20190042594
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.
    Type: Application
    Filed: June 6, 2018
    Publication date: February 7, 2019
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN, Piotr WYSOCKI
  • Publication number: 20190045028
    Abstract: Technologies for end-to-end quality of service for I/O operations include a compute device in an I/O path. The compute device receives from another of the compute devices in the I/O path, an I/O request packet. The I/O request packet includes one or more QoS deadline metadata. The QoS deadline metadata is indicative of latency information relating to a currently executing workload relative to a specified QoS. The compute device evaluates the QoS deadline metadata and assigns a priority to the I/O request packet as a function of the evaluated metadata.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Inventors: Piotr Wysocki, Maciej Andrzej Koprowski, Grzegorz Jereczek
  • Publication number: 20190042413
    Abstract: A host based Input/Output (I/O) scheduling system that improves read latency by reducing I/O collisions and improving I/O determinism of storage devices is provided. The host based storage region I/O scheduling system provides a predictable read latency using a combination of data redundancy, a host based scheduler and a write-back cache.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 7, 2019
    Inventors: Piotr WYSOCKI, Slawomir PTAK, Kapil KARKRA
  • Publication number: 20190044857
    Abstract: Examples may include an apparatus having a packet receiver to receive a packet, the packet including a packet header having a deadline and a destination network node. The apparatus includes a routing table including a current latency for a path to the destination network node for the packet. The apparatus further includes a reprioritization component to get the deadline for delivery of the packet to the destination network node, to set a remaining time for the packet to the deadline minus a current time, to subtract the current latency from the remaining time when the packet is to be routed, and to assign the packet to one of a plurality of deadline bins based at least in part on the remaining time, each deadline bin associated with one of a plurality of transmit queues, the plurality of deadline bins arranged in a deadline priority order from a highest priority to a lowest priority.
    Type: Application
    Filed: July 27, 2018
    Publication date: February 7, 2019
    Inventors: Grzegorz JERECZEK, Maciej Andrzej KOPROWSKI, Piotr WYSOCKI
  • Publication number: 20190042146
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 7, 2019
    Inventors: Michal WYSOCZANSKI, Kapil KARKRA, Piotr WYSOCKI, Anand S. RAMALINGAM
  • Publication number: 20190042114
    Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Inventors: Michael Mesnier, Kapil Karkra, Piotr Wysocki, Jonathan Hughes, Brennan Watt, Sanjeev Trika, Anand Ramalingam
  • Publication number: 20190042137
    Abstract: Technology for a nonvolatile memory (NVM) device is described. The NVM device can include a NVM interface structurally configured to communicatively couple to each of a plurality of NVM subunits of a NVM. The NVM device can include a first NVM controller communicatively coupleable to each of the plurality of NVM subunits through the NVM interface. The NVM device can include a second NVM controller communicatively coupleable to each of the plurality of NVM subunits through the NVM interface. The NVM device can include a demarcation divider dynamically positionable along the NVM interface to discretely partition the NVM interface between the first NVM controller and the second NVM controller.
    Type: Application
    Filed: February 5, 2018
    Publication date: February 7, 2019
    Inventor: Piotr Wysocki