Patents by Inventor Pirooz Parvarandeh

Pirooz Parvarandeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139578
    Abstract: An exercise equipment has a structure that can be easily collapsed for storage, and that provides improved utility due to its multiple functional capabilities and configurations thereby enabling a comprehensive set of strength exercises. The exercise equipment includes a rigid base structure that can be folded into compact form when not in use and can be configured for accessories that attach to the base structure. The exercise equipment with attached accessories combines heretofore separate pieces of equipment into one that covers a fraction of the floor space of all such separate pieces of equipment. This provides exercise equipment that is more flexible, more functional, and has a smaller footprint, all of which can be folded up for compact storage.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Pirooz Parvarandeh, Violet Parvarandeh, Bobak Parvarandeh
  • Publication number: 20240143713
    Abstract: The present invention discloses a motion vision-based multimodal authentication system and a method thereof. The system comprises several components, including an information-capturing module, an AI module, a memory unit, a processor unit, and a temporal authentication module. The system captures information data from the user and the user's surroundings, categorize the data into identity and predetermined categories, generates login credentials or authorization keys, and matches the real-time information data for user authorization.
    Type: Application
    Filed: October 28, 2023
    Publication date: May 2, 2024
    Inventors: Nima SCHEI, Pirooz PARVARANDEH, Ehsan Foroughi
  • Publication number: 20240119975
    Abstract: A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Venkatesh P. Gopinath, Pirooz Parvarandeh
  • Publication number: 20240120001
    Abstract: A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Venkatesh P. Gopinath, Pirooz Parvarandeh
  • Publication number: 20240119977
    Abstract: A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements connected between input nodes and a bitline. Each memory element includes a programmable resistor with an input connected to an input node and an output connected to the bitline. Each bank includes a feedback buffer connected to the bitline and an output node. Output nodes of banks in the same column are connected to the same column interconnect line. The initial bank in each row includes amplifiers connected between the input nodes and the memory elements, respectively. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Venkatesh P. Gopinath, Pirooz Parvarandeh
  • Publication number: 20240120004
    Abstract: A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements, each including first and second programmable resistors having inputs connected to an input node and outputs connected to first and second bitlines. In each bank, first and second feedback buffers are connected to the first and second bitlines and first and second output nodes. First and second output nodes of banks in the same column are connected to the same first and second column interconnect lines. The initial bank in each row includes amplifiers connected between the input nodes and memory elements. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Venkatesh P. Gopinath, Pirooz Parvarandeh
  • Publication number: 20240119974
    Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Venkatesh P. Gopinath, Pirooz Parvarandeh
  • Patent number: 11865398
    Abstract: An exercise equipment has a structure that can be easily collapsed for storage, and that provides improved utility due to its multiple functional capabilities and configurations thereby enabling a comprehensive set of strength exercises. The exercise equipment includes a rigid base structure that can be folded into compact form when not in use and can be configured for accessories that attach to the base structure. The exercise equipment with attached accessories combines heretofore separate pieces of equipment into one that covers a fraction of the floor space of all such separate pieces of equipment. This provides exercise equipment that is more flexible, more functional, and has a smaller footprint, all of which can be folded up for compact storage.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 9, 2024
    Assignee: i.Clarity Innovations
    Inventors: Pirooz Parvarandeh, Violet Parvarandeh, Bobak Parvarandeh
  • Publication number: 20230267998
    Abstract: Circuits that include resistive memory elements and methods of using such circuits to generate a physical unclonable function. The circuit includes a first resistive memory element, a second resistive memory element, a first transistor having a source/drain region connected to the first resistive memory element, and a second transistor having a source/drain region connected to the second resistive memory element. The circuit further includes a first inverter having an input connected to a first node between the first transistor and the first resistive memory element, and a second inverter having an input connected to a second node between the second transistor and the second resistive memory element.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: Pirooz Parvarandeh, Periyapatna G. Venkatesh
  • Publication number: 20230260561
    Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Applicant: GlobalFoundries U.S. Inc.
    Inventors: Venkatesh P. Gopinath, Pirooz Parvarandeh
  • Patent number: 11602465
    Abstract: A diaper wetness detection system includes a diaper, a wetness sensor, an RFID unit, and a transceiver unit. The RFID unit is a battery-less device that receives an interrogation signal transmitted by the transceiver unit. The RFID unit or the transceiver unit are configured to determine if a measurable characteristic, as sensed by the wetness sensor, indicates if the diaper is wet. The measurable characteristic can be a voltage or current indicative of a resistance, capacitance, or impedance at an area sensed by the wetness sensor. The value of the measurable characteristic is different when the diaper is wet versus dry. Comparing the measurable characteristic value to a threshold value or to one or more previously sensed measurable characteristic values enables a determination to be made as to whether or not the diaper is wet. The RFID unit can be detachably coupled to the diaper for simple attachment and removal.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: March 14, 2023
    Assignee: i.Clarity Innovations LLC
    Inventor: Pirooz Parvarandeh
  • Publication number: 20220250056
    Abstract: Toward forming a single hybrid biosensing-imaging system that can operate inside an incubator, structures and methods are directed to placing modular and removable biosensors and biocompatible interfaces in 3D transparent test wells that contain biological samples. The technology enables continuous monitoring of multiple simultaneous parameters and functions of a living cell or cell clusters such as alterations of cellular ligands, physicochemical biomarkers, phenotypes, and/or extracellular compositions upon interactions with analytes or during progressions. Methods of capturing and analyzing direct orthogonal information from biological samples in 2D and 3D, which are conducive to generating new insights are presented.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 11, 2022
    Inventors: Mandana Veiseh, Pirooz Parvarandeh, S. Bahram Bahrami, Oliver Peter King-Smith, Todd S. Rutherford, Aaron Peter Schellenberg, Timothy Scott Edward Hiller
  • Patent number: 11338294
    Abstract: Toward forming a single hybrid biosensing-imaging system that can operate inside an incubator, structures and methods are directed to placing modular and removable biosensors and biocompatible interfaces in 3D transparent test wells that contain biological samples. The technology enables continuous monitoring of multiple simultaneous parameters and functions of a living cell or cell clusters such as alterations of cellular ligands, physicochemical biomarkers, phenotypes, and/or extracellular compositions upon interactions with analytes or during progressions. Methods of capturing and analyzing direct orthogonal information from biological samples in 2D and 3D, which are conducive to generating new insights are presented.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 24, 2022
    Assignee: Polybiomics, Inc.
    Inventors: Mandana Veiseh, Pirooz Parvarandeh, S. Bahram Bahrami, Oliver Peter King-Smith, Todd S. Rutherford, Aaron Peter Schellenberg, Timothy Scott Edward Hiller
  • Patent number: 11199454
    Abstract: A temperature measurement footprint device, a mobile temperature measurement device, and a method for determining a temperature measurement footprint are described. In an implementation, a temperature measurement footprint device includes a thermopile configured to measure a temperature of an object; a camera configured to capture an image of the object, the camera disposed proximate to and in communication with the thermopile; and a light source configured to illuminate the object, the light source disposed proximate to and in communication with the thermopile and the camera.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: December 14, 2021
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventor: Pirooz Parvarandeh
  • Patent number: 10973353
    Abstract: An entry device that is attachable to a door that pivots relative to a door frame to separate an outer area from an inner area is disclosed. The device has a compartment made of a flexible material having a first side and a second side. The flexible material has a front surface that faces the outer area and a back surface that extends into the inner area. At least one first attachment point is disposed along the first side that attaches the compartment to the door and at least one second attachment point is disposed along the second side that attaches the compartment to the door frame. According to the present invention, upon opening of the door, the compartment is configured to allow partial entry of an object to the inner area and prevent full entry by a person from the outer area.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 13, 2021
    Assignee: i.Clarity Innovations LLC
    Inventor: Pirooz Parvarandeh
  • Publication number: 20210041392
    Abstract: A nanopore cell may include a well having a working electrode at a bottom of the well. The well may be formed within a dielectric layer, where the sidewalls of the well may be formed of the dielectric or other materials coating the walls of the dielectric layer. Various materials having different hydrophobicity and hydrophilicity can be used to provide desired properties of the cell. The nanopore in the nanopore cell can be inserted in a membrane formed over the well. Various techniques can be used for providing a desired shape and other properties e.g., of materials and processes for forming the well.
    Type: Application
    Filed: July 21, 2020
    Publication date: February 11, 2021
    Inventors: Wing Au, Guojun Chen, Ronald L. Cicero, John Foster, Kenneth A. Honer, Marowen Ng, Pirooz Parvarandeh
  • Patent number: 10896145
    Abstract: A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 19, 2021
    Assignee: BEDROCK AUTOMATION PLATFORMS INC.
    Inventors: James G. Calvin, Albert Rooyakkers, Pirooz Parvarandeh
  • Patent number: 10739299
    Abstract: A nanopore cell may include a well having a working electrode at a bottom of the well. The well may be formed within a dielectric layer, where the sidewalls of the well may be formed of the dielectric or other materials coating the walls of the dielectric layer. Various materials having different hydrophobicity and hydrophilicity can be used to provide desired properties of the cell. The nanopore in the nanopore cell can be inserted in a membrane formed over the well. Various techniques can be used for providing a desired shape and other properties e.g., of materials and processes for forming the well.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: August 11, 2020
    Assignee: Roche Sequencing Solutions, Inc.
    Inventors: Ronald L. Cicero, Kenneth A. Honer, John Foster, Pirooz Parvarandeh, Marowen Ng, Wing Au, Guojun Chen
  • Publication number: 20200246791
    Abstract: Techniques for replacing nanopores within a nanopore based sequencing chip are provided. A first electrolyte solution is added to the external reservoir of the sequencing chip, introducing an osmotic imbalance between the reservoir and the well chamber located on the opposite side of a lipid bilayer membrane. The osmotic imbalance causes the membrane to change shape, and a nanopore within the membrane to be ejected. A second electrolyte solution is then added to the external reservoir to provide replacement nanopores and to restore the membrane shape. The replacement nanopores can be inserted into the membrane, effectively replacing the initial pore without causing the destruction of the membrane.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Geoffrey Barrall, Takeshi Harada, Jason Komadina, Pirooz Parvarandeh, Charlotte Yang
  • Publication number: 20200170432
    Abstract: An entry device that is attachable to a door that pivots relative to a door frame to separate an outer area from an inner area is disclosed. The device has a compartment made of a flexible material having a first side and a second side. The flexible material has a front surface that faces the outer area and a back surface that extends into the inner area. At least one first attachment point is disposed along the first side that attaches the compartment to the door and at least one second attachment point is disposed along the second side that attaches the compartment to the door frame. According to the present invention, upon opening of the door, the compartment is configured to allow partial entry of an object to the inner area and prevent full entry by a person from the outer area.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 4, 2020
    Applicant: i.Clarity LLC
    Inventor: Pirooz PARVARANDEH