Patents by Inventor Po-Chun Liu

Po-Chun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374136
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20220181418
    Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.
    Type: Application
    Filed: October 18, 2021
    Publication date: June 9, 2022
    Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
  • Patent number: 11340662
    Abstract: A portable electronic device including a first body, a second body, a hinge mechanism, a control unit, a sensor unit, a sterilization module, and a shielding module, is provided. The first body has a first inner surface. The second body has a second inner surface. The hinge mechanism is connected between the first body and the second body. The control unit is disposed in the first body or the second body. The sensor unit is disposed in the first body or the second body and coupled to the control unit. The sterilization module is disposed at the hinge mechanism and coupled to the control unit, the sterilization module is configured to generate light for sterilization and disinfection. The shielding module is disposed on the hinge mechanism and the shielding module can move relative to the hinge mechanism.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: May 24, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yi-Chun Lin, Ya-Hui Tseng, I-Kai Liu, Po-Ching Chiang, Chien-Lun Sun, Yen-Kang Chen, Jih-Houng Lee, Chih-Chien Liu
  • Publication number: 20220157605
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien-Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
  • Patent number: 11329148
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 11306529
    Abstract: A space adjustment system and a control method thereof are provided. The space adjustment system includes a body, at least one door leaf, at least one motor, and a control circuit. The door leaf is movably disposed at the body. The door panel of each door leaf includes a panel. The motor can drive the motion of the door leaf. The control circuit is coupled with the panel of the door leaf and motor. The control circuit controls the motor to drive the door leaf, and adjusts the transparency or display function of the panel on the corresponding door leaf in response to a location of the door leaf. Accordingly, multiple space type can be created.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 19, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ruei-Hong Hong, Wen-Yi Chiu, Wei-Jun Wang, Po-Chun Liu
  • Patent number: 11208793
    Abstract: A sanitary equipment with a water supply system, a water route system, and a hand washing table are provided. The sanitary equipment includes a machine having a machine water outlet; a movable hand washing table pivoted on the machine and located below the machine water outlet, the movable hand washing table being capable of opening or retracting with respect to the machine; and a water route system disposed in the machine and connected to the machine water outlet to discharge potable water and non-potable water from the machine water outlet.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 28, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Chun Liu, Wen-Yi Chiu, Pin-Hsing Lee
  • Publication number: 20210391435
    Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu
  • Publication number: 20210376086
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Application
    Filed: September 29, 2020
    Publication date: December 2, 2021
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20210375669
    Abstract: A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The method includes depositing a dielectric layer on a substrate, forming a trench within the dielectric layer and the substrate, forming an epitaxial structure within the trench, and forming a barrier layer with first and second layer portions. The first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure. The method further includes forming a capping layer on the epitaxial structure and adjacent to the barrier layer, selectively doping regions of the epitaxial structure and the capping layer, selectively forming a silicide layer on the doped regions, depositing an etch stop layer on the silicide layer, and forming conductive plugs on the silicide layer through the etch stop layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun LIU, Eugene I-Chun CHEN, Chun-Kai LAN
  • Publication number: 20210167236
    Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.
    Type: Application
    Filed: January 14, 2021
    Publication date: June 3, 2021
    Inventors: Chih-Ming Chen, Lee-Chuan Tseng, Ming Chyi Liu, Po-Chun Liu
  • Patent number: 11014111
    Abstract: A sanitary equipment and a control method thereof are provided. The sanitary equipment includes a main body having an opining, a cover body movably disposed at the main body, an electric motor driving the cover body to move, an auxiliary apparatus disposed at the main body and a control circuit coupled to the electric motor and the auxiliary apparatus. In response to operation or wireless remote control, the control circuit controls the electric motor to drive the cover body to open the opening and turn on the auxiliary apparatus in a first process. In a second process, the control circuit controls the electric motor to drive the cover body to close the opening, and turns off the auxiliary apparatus at the same time. Sequences, numbers of steps of the first process and the second process are different. Accordingly, the sanitary equipment with multiple functions and convenient use is provided.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 25, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Jun Wang, Ruei-Hong Hong, Wen-Yi Chiu, Po-Chun Liu, Chia-Shin Weng, Shi-Kuan Chen
  • Patent number: 10991819
    Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun Liu, Chung-Yi Yu, Chi-Ming Chen, Chen-Hao Chiang
  • Publication number: 20210098524
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor in which a device layer has high crystalline quality. According to some embodiments, a hard mask layer is deposited covering a substrate. A first etch is performed into the hard mask layer and the substrate to form a cavity. A second etch is performed to remove crystalline damage from the first etch and to laterally recess the substrate in the cavity so the hard mask layer overhangs the cavity. A sacrificial layer is formed lining cavity, a blanket ion implantation is performed into the substrate through the sacrificial layer, and the sacrificial layer is removed. An interlayer is epitaxially grown lining the cavity and having a top surface underlying the hard mask layer, and a device layer is epitaxially grown filling the cavity over the interlayer. A photodetector is formed in the device layer.
    Type: Application
    Filed: June 10, 2020
    Publication date: April 1, 2021
    Inventors: Po-Chun Liu, Yung-Chang Chang, Eugene I-Chun Chen
  • Publication number: 20210074755
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Inventors: Po-Chun Liu, Chung-Yi Yu, Eugene Chen
  • Patent number: 10937900
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first III-V layer over the substrate, having a first band gap, and a second III-V layer over the first III-V layer, having a second band gap. The second III-V layer includes a first surface in contact with the first III-V layer and a second surface opposite to the first surface. The second band gap at the second surface is greater than the second band gap at the first surface. The present disclosure also provides a manufacturing method of the aforesaid semiconductor structure.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Yao-Chung Chang, Jiun-Lei Jerry Yu, Chen-Hao Chiang, Chung-Yi Yu
  • Publication number: 20210050209
    Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.
    Type: Application
    Filed: November 4, 2020
    Publication date: February 18, 2021
    Inventors: Po-Chun LIU, Chung-Chieh HSU, Chi-Ming CHEN, Chung-Yi YU, Chen-Hao CHIANG, Min-Chang CHING
  • Publication number: 20210036140
    Abstract: A semiconductor device includes a doped substrate and a seed layer in direct contact with the substrate. The seed layer includes a first seed sublayer having a first lattice structure. The first seed layer is doped with carbon. The seed layer further includes a second seed sublayer over the first see layer, wherein the second seed layer has a second lattice structure. The semiconductor device further includes a graded layer in direct contact with the seed layer. The graded layer includes a first graded sublayer including AlGaN having a first Al:Ga ratio; a second graded sublayer including AlGaN having a second Al:Ga ratio different from the first Al:Ga ratio; and a third graded sublayer over including AlGaN having a third Al:Ga ratio different from the second Al:Ga ratio. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
  • Publication number: 20210028016
    Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 28, 2021
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI
  • Patent number: D916716
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 20, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ruei-Hong Hong, Wen-Yi Chiu, Po-Chun Liu, Wei-Jun Wang