Patents by Inventor Po-Chun Yeh
Po-Chun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250137773Abstract: A film thickness measurement device includes a spectroscopic ellipsometer, and the spectroscopic ellipsometer includes a projection module and a light receiving module. The projection module is configured to project a multi-wavelength polarized light onto a thin film. The projection module includes a light source and a polarization state generator. The light receiving module includes a polarization analyzer and an optical detector. The polarization analyzer is configured to screen out a multi-wavelength polarized reflection light according to reflection of the multi-wavelength polarized light by the thin film. The optical detector is configured to receive the multi-wavelength polarized reflection light. The optical detector includes at least one optical splitting unit, at least two optical filtering units and at least two optical detection units.Type: ApplicationFiled: December 13, 2023Publication date: May 1, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Shih-Hsiang LAI, Fu-Cheng YANG, Fu-Ching TUNG, Hsuan-Fu WANG, Po-Chun YEH
-
Publication number: 20250107332Abstract: An all-oxide transistor structure includes a substrate, a first transistor, a second transistor, a third transistor and a fourth transistor. The substrate has an upper surface. The first transistor is disposed on the upper surface of the substrate. The second transistor is disposed on the upper surface of the substrate, wherein the second transistor is electrically connected to the first transistor. The third transistor is electrically connected to the second transistor and overlapped with the second transistor in a first direction, wherein the first direction is parallel to a normal direction of the upper surface of the substrate. The fourth transistor is disposed on the upper surface of the substrate, wherein the fourth transistor is electrically connected to the first transistor, the second transistor and the third transistor.Type: ApplicationFiled: December 5, 2024Publication date: March 27, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Po-Chun YEH, Sih-Han LI, Jian-Wei SU
-
Publication number: 20250098414Abstract: An all-oxide transistor structure includes a substrate having an upper surface and a first transistor disposed on the upper surface of the substrate. The first transistor includes a first drain, a first dielectric layer, a first source, at least one first opening and a first channel layer. The first drain, the first dielectric layer and the first source are disposed on the substrate along a first direction, and the first direction is parallel to a normal direction of the upper surface. The first opening passes through the first drain, the first dielectric layer and the first source along the first direction. The first channel layer, the first gate dielectric layer and the first gate are disposed in the first opening. The first gate dielectric layer is disposed on the first channel layer. The first gate is disposed on the first gate dielectric layer.Type: ApplicationFiled: December 27, 2023Publication date: March 20, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Haw-Tyng HUANG, Po-Chun YEH, Hsien-Yi LIAO, Yao-Cing HAN
-
Publication number: 20250063772Abstract: A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.Type: ApplicationFiled: November 7, 2024Publication date: February 20, 2025Applicant: Industrial Technology Research InstituteInventors: Po-Chun Yeh, Hsiang-Chun Wang
-
Patent number: 12096657Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.Type: GrantFiled: October 18, 2021Date of Patent: September 17, 2024Assignee: Apple Inc.Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
-
Publication number: 20240210995Abstract: A display may have a stretchable portion with hermetically sealed rigid pixel islands. A flexible interconnect region may be interposed between the hermetically sealed rigid pixel islands. The hermetically sealed rigid pixel islands may include organic light-emitting diode (OLED) pixels. A conductive cutting structure may have an undercut that causes a discontinuity in a conductive OLED layer to mitigate lateral leakage. The conductive cutting structure may also be electrically connected to a cathode for the OLED pixels and provide a cathode voltage to the cathode. First and second inorganic passivation layers may be formed over the OLED pixels. Multiple discrete portions of an organic inkjet printed layer may be interposed between the first and second inorganic passivation layers.Type: ApplicationFiled: October 10, 2023Publication date: June 27, 2024Inventors: Prashant Mandlik, Bhadrinarayana Lalgudi Visweswaran, Mahendra Chhabra, Chia-Hao Chang, Shiyi Liu, Siddharth Harikrishna Mohan, Zhen Zhang, Han-Chieh Chang, Yi Qiao, Yue Cui, Tyler R Kakuda, Michael Vosgueritchian, Sudirukkuge T. Jinasundera, Warren S Rieutort-Louis, Tsung-Ting Tsai, Jae Won Choi, Jiun-Jye Chang, Jean-Pierre S Guillou, Rui Liu, Po-Chun Yeh, Chieh Hung Yang, Ankit Mahajan, Takahide Ishii, Pei-Ling Lin, Pei Yin, Gwanwoo Park, Markus Einzinger, Martijn Kuik, Abhijeet S Bagal, Kyounghwan Kim, Jonathan H Beck, Chiang-Jen Hsiao, Chih-Hao Kung, Chih-Lei Chen, Chih-Yu Chung, Chuan-Jung Lin, Jung Yen Huang, Kuan-Chi Chen, Shinya Ono, Wei Jung Hsieh, Wei-Chieh Lin, Yi-Pu Chen, Yuan Ming Chiang, An-Di Sheu, Chi-Wei Chou, Chin-Fu Lee, Ko-Wei Chen, Kuan-Yi Lee, Weixin Li, Shin-Hung Yeh, Shyuan Yang, Themistoklis Afentakis, Asli Sirman, Baolin Tian, Han Liu
-
Publication number: 20240145559Abstract: A transistor structure includes a substrate, a source electrode, a drain electrode, a protective layer and a gate electrode. The source electrode and the drain electrode are provided on the substrate. The protective layer is provided on the substrate. The protective layer is provided between the source electrode and the drain electrode. The protective layer includes a SiNx layer and a SiOx layer. The SiOx layer is provided on the substrate, the SiNx layer is provided on the SiOx layer, and a through hole of the protective layer is formed to extend through the SiNx layer and the SiOx layer. The gate electrode is provided in the through hole, and the gate electrode is separated from at least part of the SiOx layer so as to form an air gap therebetween.Type: ApplicationFiled: December 21, 2022Publication date: May 2, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chang-Yan HSIEH, Po-Tsung TU, Jui-Chin CHEN, Hui-Yu CHEN, Po-Chun YEH
-
Patent number: 11910654Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk, the display may include active and/or passive leakage-mitigating structures. The passive leakage-mitigating structures may have an undercut that causes discontinuities in the overlying OLED layers. Active leakage-mitigating structures may include a conductive layer (e.g., a conductive ring) that drains leakage current to ground. Alternatively, the active leakage-mitigating structures may include a gate electrode modulator with a variable voltage that stops the current flow laterally.Type: GrantFiled: August 5, 2021Date of Patent: February 20, 2024Assignee: Apple Inc.Inventors: Po-Chun Yeh, Jiun-Jye Chang, Doh-Hyoung Lee, Caleb Coburn, Niva A. Ran, Ching-Sang Chuang, Themistoklis Afentakis, Chuan-Jung Lin, Jung Yen Huang, Lei Yuan
-
Patent number: 11856789Abstract: A ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer. The ferroelectric composite layer includes a first electrode layer, a second electrode layer, a ferroelectric layer and an antiferroelectric layer. The first electrode layer is opposite to the second electrode layer, and the ferroelectric layer and the antiferroelectric layer are disposed between the first electrode layer and the second electrode layer.Type: GrantFiled: July 6, 2021Date of Patent: December 26, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-De Lin, Po-Chun Yeh, Pei-Jer Tzeng
-
Publication number: 20230147806Abstract: A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.Type: ApplicationFiled: December 8, 2021Publication date: May 11, 2023Applicant: Industrial Technology Research InstituteInventors: Shang-Chun Chen, Po-Chun Yeh, Pei-Jer Tzeng
-
Patent number: 11549843Abstract: An ultrasonic sensing device includes a housing, a piezoelectric assembly, a board and a plurality of fixing members. The housing includes a connecting board being a metal board and a supporting shell being a plastic member. The supporting shell includes a bottom wall opposite to a disposing opening of the connecting board and a surrounding side wall integrally surrounding and connecting to the bottom wall. The surrounding side wall encloses a portion of the connecting board. The piezoelectric assembly includes an encapsulating body and a piezoelectric sheet enclosed by the encapsulating body. The encapsulating body is disposed on the bottom wall and surrounded by the surrounding side wall. The piezoelectric sheet has a sensing surface exposed to the encapsulating body and facing the bottom wall. The fixing members fix the board on the connecting board, thereby pressing the sensing surface of the piezoelectric sheet to the bottom wall.Type: GrantFiled: April 14, 2020Date of Patent: January 10, 2023Assignee: Qian Jun Technology Ltd.Inventors: Yu-Yen Fu, Po-Chun Yeh, Dong-Fu Chen
-
Publication number: 20220359549Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer.Type: ApplicationFiled: July 6, 2021Publication date: November 10, 2022Inventors: Yu-De LIN, Po-Chun YEH, Pei-Jer TZENG
-
Patent number: 11476404Abstract: An ultrasonic sensing device includes a housing, a piezoelectric assembly, a board and a plurality of fixing members. The housing includes a bottom wall, a top wall and a surrounding side wall connected between the top wall and the bottom wall. The piezoelectric assembly includes an encapsulating body and a piezoelectric sheet, wherein at least a portion of the piezoelectric sheet is enclosed by the encapsulating body and has a sensing surface exposed to the encapsulating body and facing the bottom wall. The board is disposed on the top wall of the housing and has a pressing surface facing the encapsulating body and the top wall. The plurality of fixing members is configured to fix the board to the top wall of the housing to press the board to the encapsulating body of the piezoelectric assembly, thereby pressing the sensing surface of the piezoelectric sheet to the bottom wall.Type: GrantFiled: February 20, 2020Date of Patent: October 18, 2022Assignee: Qian Jun Technology Ltd.Inventors: Chi-Shen Lee, Yu-Yen Fu, Po-Chun Yeh, Dong-Fu Chen, Chih-Wen Cheng, Chi-Lin Huang, Yu-Ping Yen
-
Publication number: 20220181418Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.Type: ApplicationFiled: October 18, 2021Publication date: June 9, 2022Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
-
Patent number: 11217661Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.Type: GrantFiled: April 7, 2020Date of Patent: January 4, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-De Lin, Heng-Yuan Lee, Po-Chun Yeh, Chih-Yao Wang, Hsin-Yun Yang
-
Patent number: 11121263Abstract: Display panels with hydrogen trap layers are described. The hydrogen trap layers may be incorporated into a variety of locations to getter or block hydrogen diffusion into the semiconductor oxide layer of an oxide transistor.Type: GrantFiled: January 17, 2020Date of Patent: September 14, 2021Assignee: Apple Inc.Inventors: Jehun Lee, Ching-Sang Chuang, Hirokazu Yamagata, Jiun-Jye Chang, Kenny Kim, Po-Chun Yeh, Shih Chang Chang, Ting-Kuo Chang
-
Publication number: 20210242304Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.Type: ApplicationFiled: April 7, 2020Publication date: August 5, 2021Inventors: Yu-De LIN, Heng-Yuan LEE, Po-Chun YEH, Chih-Yao WANG, Hsin-Yun YANG
-
Patent number: 11079356Abstract: An ultrasonic sensing apparatus includes an accommodating shell and at least one detection device. The accommodating shell includes a base and a convex portion connected to the base. A side of the base has a first detection opening toward a first direction, and a side of the convex portion has a second detection opening toward a second direction. Each of the at least one detection device is disposed in the base or the convex portion of the accommodating shell and includes a board, a piezoelectric assembly, a housing and a plurality of fixing members. The plurality of fixing members are configured to fix the board on the top wall of the housing to press the board to the encapsulating body of the piezoelectric assembly, thereby pressing the piezoelectric sheet to the bottom wall.Type: GrantFiled: April 14, 2020Date of Patent: August 3, 2021Assignee: Qian Jun Technology Ltd.Inventors: Yu-Yen Fu, Po-Chun Yeh, Dong-Fu Chen
-
Publication number: 20210174855Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode layer having a dominant crystallographic orientation of (110) or (220), a second electrode layer opposite the first electrode layer, wherein the second electrode layer has a dominant crystallographic orientation of (110) or (220), and a ferroelectric layer disposed between the first electrode layer and the second electrode layer, wherein the ferroelectric layer has a dominant crystallographic orientation of (111).Type: ApplicationFiled: June 19, 2020Publication date: June 10, 2021Inventors: Yu-De LIN, Heng-Yuan LEE, Po-Chun YEH, Hsin-Yun YANG
-
Patent number: 11017830Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode layer having a dominant crystallographic orientation of (110) or (220), a second electrode layer opposite the first electrode layer, wherein the second electrode layer has a dominant crystallographic orientation of (110) or (220), and a ferroelectric layer disposed between the first electrode layer and the second electrode layer, wherein the ferroelectric layer has a dominant crystallographic orientation of (111).Type: GrantFiled: June 19, 2020Date of Patent: May 25, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-De Lin, Heng-Yuan Lee, Po-Chun Yeh, Hsin-Yun Yang
