Patents by Inventor Po-Hao Lee

Po-Hao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230131308
    Abstract: A memory device includes a computing-in-memory macro and a clock generating circuit. The computing-in-memory macro is configured to perform in-memory computing based on a first clock signal. The clock generating circuit is arranged within the computing-in-memory macro and configured to generate the first clock signal. A frequency of the first clock signal is modified according to a condition of the computing-in-memory macro to cause the first clock signal to conform to an operation speed of the in-memory computing.
    Type: Application
    Filed: May 12, 2022
    Publication date: April 27, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu LEE, Po-Hao LEE, Yi-Chun SHIH, YU-DER CHIH
  • Patent number: 11594269
    Abstract: A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih
  • Publication number: 20220398067
    Abstract: A multiply-accumulate (MAC) device for compute-in-memory (CIM) includes an input driver configured to provide a plurality of input signals including a first input signal and a second input signal. A lookup table (LUT) stores or accesses a plurality of CIM weight signals including a first CIM weight signal and a second CIM weight signal. The LUT is configured to receive the first input signal and the second input signal and provide a sum output based on the first and second input signals and the first and second CIM weight signals.
    Type: Application
    Filed: December 23, 2021
    Publication date: December 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Po-Hao Lee, Yi-Chun Shih, Yu-Der Chih
  • Publication number: 20220269483
    Abstract: A compute-in memory (CIM) device is configured to determine at least one input according to a type of an application and at least one weight according to a training result or a configuration of a user. The CIM device performs a bit-serial multiplication based on the input and the weight, from a most significant bit (MSB) of the input to a least significant bit (LSB) of the input to obtain a result according to a plurality of partial-products. A first partial-sum of a first bit of the input is left shifted one bit and then added with a second partial-product of a second bit of the input to obtain a second partial-sum of the second bit. The second bit is one bit after the first bit, and the result is output by the CIM device.
    Type: Application
    Filed: December 21, 2021
    Publication date: August 25, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh-Pu Lo, Po-Hao Lee, Yi-Chun Shih
  • Publication number: 20220262421
    Abstract: The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Inventors: Yen-An Chang, Po-Hao Lee, Yi-Chun Shih
  • Publication number: 20220253282
    Abstract: In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.
    Type: Application
    Filed: November 22, 2021
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Po-Hao Lee, Yi-Chun Shih, Yu-Der Chih
  • Publication number: 20220244916
    Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.
    Type: Application
    Filed: July 28, 2021
    Publication date: August 4, 2022
    Inventors: Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Yu-Der Chih, Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao
  • Patent number: 11355173
    Abstract: The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-An Chang, Po-Hao Lee, Yi-Chun Shih
  • Publication number: 20220157377
    Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
    Type: Application
    Filed: February 3, 2022
    Publication date: May 19, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih
  • Publication number: 20220068381
    Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 3, 2022
    Inventors: Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih
  • Patent number: 11264093
    Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih
  • Publication number: 20220019407
    Abstract: A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements.
    Type: Application
    Filed: March 16, 2021
    Publication date: January 20, 2022
    Inventors: Yu-Der CHIH, Hidehiro FUJIWARA, Yi-Chun SHIH, Po-Hao LEE, Yen-Huei CHEN, Chia-Fu LEE, Jonathan Tsung-Yung CHANG
  • Patent number: 11211142
    Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Chun Shih, Po-Hao Lee, Chia-Fu Lee, Yu-Der Chih, Yu-Lin Chen
  • Publication number: 20210398579
    Abstract: A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.
    Type: Application
    Filed: April 5, 2021
    Publication date: December 23, 2021
    Inventors: Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih
  • Patent number: 11189325
    Abstract: A device includes several first switching units and several second switching units. Each of the first switching units transmits in response to a first select signal, an auxiliary signal. Each of the second switching units is coupled to a corresponding one of the first switching units and transmits in response to a second select signal, a write voltage to a corresponding one of multiple circuit cells. The second switching units are coupled with each other in a node which receives the write voltage.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao Lee, Yi-Chun Shih
  • Publication number: 20210358532
    Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
  • Patent number: 11139017
    Abstract: An integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-An Chang, Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Yu-Der Chih
  • Patent number: 11081155
    Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
  • Publication number: 20210201975
    Abstract: The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.
    Type: Application
    Filed: October 27, 2020
    Publication date: July 1, 2021
    Inventors: Yen-An Chang, Po-Hao Lee, Yi-Chun Shih
  • Publication number: 20210174841
    Abstract: A device includes several first switching units and several second switching units. Each of the first switching units transmits in response to a first select signal, an auxiliary signal. Each of the second switching units is coupled to a corresponding one of the first switching units and transmits in response to a second select signal, a write voltage to a corresponding one of multiple circuit cells. The second switching units are coupled with each other in a node which receives the write voltage.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 10, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao LEE, Yi-Chun SHIH