Patents by Inventor Po-Hao Lee
Po-Hao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210142840Abstract: An integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.Type: ApplicationFiled: March 5, 2020Publication date: May 13, 2021Inventors: Yen-An Chang, Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Yu-Der Chih
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Patent number: 10937467Abstract: A device includes a circuit cell, a first switching unit, and a second switching unit. The first switching unit is configured to output an auxiliary signal. The second switching unit is coupled between the first switching unit and the circuit cell, and configured to transmit a write voltage and an auxiliary signal to the circuit cell.Type: GrantFiled: October 22, 2019Date of Patent: March 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao Lee, Yi-Chun Shih
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Publication number: 20200227133Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.Type: ApplicationFiled: March 25, 2020Publication date: July 16, 2020Inventors: Yi-Chun Shih, Po-Hao Lee, Chia-Fu Lee, Yu-Der Chih, Yu-Lin Chen
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Patent number: 10636511Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.Type: GrantFiled: July 25, 2018Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Chun Shih, Po-Hao Lee, Chia-Fu Lee, Yu-Der Chih, Yu-Lin Chen
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Publication number: 20200051598Abstract: A device includes a circuit cell, a first switching unit, and a second switching unit. The first switching unit is configured to output an auxiliary signal. The second switching unit is coupled between the first switching unit and the circuit cell, and configured to transmit a write voltage and an auxiliary signal to the circuit cell.Type: ApplicationFiled: October 22, 2019Publication date: February 13, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao LEE, Yi-Chun SHIH
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Publication number: 20190385656Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.Type: ApplicationFiled: June 4, 2019Publication date: December 19, 2019Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
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Patent number: 10490233Abstract: A device includes a circuit cell, a voltage regulator, a first switching unit, a second switching unit, and a third switching unit. The voltage regulator is configured to output a write voltage. The first switching unit is configured to generate, in response to a control voltage, a current represented by an auxiliary signal. The second switching unit is configured to receive the auxiliary signal, and to turn on to transmit the auxiliary signal to the circuit cell. The third switching unit is configured to receive the write voltage, and to turn on to transmit the write voltage to the circuit cell.Type: GrantFiled: September 17, 2018Date of Patent: November 26, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao Lee, Yi-Chun Shih
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Publication number: 20190035487Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.Type: ApplicationFiled: July 25, 2018Publication date: January 31, 2019Inventors: Yi-Chun Shih, Po-Hao Lee, Chia-Fu Lee, Yu-Der Chih, Yu-Lin Chen
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Publication number: 20190019541Abstract: A device includes a circuit cell, a voltage regulator, a first switching unit, a second switching unit, and a third switching unit. The voltage regulator is configured to output a write voltage. The first switching unit is configured to generate, in response to a control voltage, a current represented by an auxiliary signal. The second switching unit is configured to receive the auxiliary signal, and to turn on to transmit the auxiliary signal to the circuit cell. The third switching unit is configured to receive the write voltage, and to turn on to transmit the write voltage to the circuit cell.Type: ApplicationFiled: September 17, 2018Publication date: January 17, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao LEE, Yi-Chun SHIH
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Patent number: 10083724Abstract: A device includes a circuit cell, a voltage regulator, and an auxiliary signal generator. The voltage regulator is configured to output a write voltage. The auxiliary signal generator is configured to generate an auxiliary signal according to a reference voltage and a reference current, and to transmit the auxiliary signal and the write voltage to the circuit cell according to select signals.Type: GrantFiled: July 17, 2017Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao Lee, Yi-Chun Shih
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Patent number: 10014469Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.Type: GrantFiled: February 21, 2017Date of Patent: July 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Po-Hao Lee, Chung-Cheng Chou, Wen-Ting Chu
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Patent number: 9985203Abstract: The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack.Type: GrantFiled: November 15, 2013Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jonathan Tehan Chen, Chung-Cheng Chou, Po-Hao Lee, Kuo-Chi Tu
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Patent number: 9977441Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.Type: GrantFiled: April 7, 2016Date of Patent: May 22, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Cheng Chou, Po-Hao Lee
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Patent number: 9922962Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.Type: GrantFiled: April 12, 2017Date of Patent: March 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Cheng Chou, Po-Hao Lee, Jonathan Tehan Chen
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Publication number: 20170323669Abstract: A device includes a circuit cell, a voltage regulator, and an auxiliary signal generator. The voltage regulator is configured to output a write voltage. The auxiliary signal generator is configured to generate an auxiliary signal according to a reference voltage and a reference current, and to transmit the auxiliary signal and the write voltage to the circuit cell according to select signals.Type: ApplicationFiled: July 17, 2017Publication date: November 9, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao LEE, Yi-Chun SHIH
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Patent number: 9728231Abstract: A device includes a voltage regulator, an auxiliary signal generator, and a circuit cell. The voltage regulator is configured to output a write voltage. The auxiliary signal generator is configured to output an auxiliary signal. The circuit cell is configured to receive both of the write voltage and the auxiliary signal according to a first select signal and a second select signal.Type: GrantFiled: May 3, 2016Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao Lee, Yi-Chun Shih
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Publication number: 20170221862Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.Type: ApplicationFiled: April 12, 2017Publication date: August 3, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Cheng CHOU, Po-Hao LEE, Jonathan Tehan CHEN
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Publication number: 20170162786Abstract: The present disclosure provides a semiconductor structure Which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.Type: ApplicationFiled: February 21, 2017Publication date: June 8, 2017Inventors: PO-HAO LEE, CHUNG-CHENG CHOU, WEN-TING CHU
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Patent number: 9659647Abstract: A circuit for programming a memory cell having a programmable resistance includes a switch. The circuit is configured to apply a programming voltage to the memory cell when the switch is in a first state. The circuit is configured to apply a programming current to the memory cell when the switch is in a second state. The resistance of the memory cell changes from a first resistance state to a second resistance state based on the application of the programming voltage or the programming current to the memory cell.Type: GrantFiled: February 5, 2016Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Po-Hao Lee, Chung-Cheng Chou, Chia-Fu Lee
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Patent number: 9625186Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.Type: GrantFiled: August 29, 2013Date of Patent: April 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Cheng Chou, Po-Hao Lee, Jonathan Tehan Chen