Patents by Inventor Po-Hao Lee
Po-Hao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9620209Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.Type: GrantFiled: August 16, 2016Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Chun Shih, Chung-Cheng Chou, Po-Hao Lee
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Patent number: 9608204Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.Type: GrantFiled: September 9, 2013Date of Patent: March 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Po-Hao Lee, Chung-Cheng Chou, Wen-Ting Chu
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Publication number: 20160358651Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.Type: ApplicationFiled: August 16, 2016Publication date: December 8, 2016Inventors: YI-CHUN SHIH, CHUNG-CHENG CHOU, PO-HAO LEE
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Patent number: 9478287Abstract: Circuits and methods for detecting write operation and limiting cell current in resistive random access memory (RRAM or ReRAM) cells are provided. RRAM cells can include a select transistor and a programmable resistor. Current can flow through the programmable resistor responsive to word line voltage VWL applied to the gate of the select transistor and a bit line voltage VBL applied to the source of the select transistor. Responsive to the current, the programmable resistor can change between relatively high and low resistances (“SET”), or between relatively low and high resistances (“RESET”). It can be desirable to accurately characterize the resistance of the programmable resistor, that is, to accurately detect write operations such as SET or RESET. Additionally, it can be undesirable for the current to exceed a certain value (“over-SET”). The present circuits and methods can facilitate detecting write operations or limiting current, or both, in an RRAM cell.Type: GrantFiled: January 29, 2015Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chung-Cheng Chou, Yi-Chun Shih, Po-Hao Lee
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Patent number: 9472245Abstract: A device includes first and second current mirrors electrically connected to reference and cell current sources of a memory array. A first inverter is electrically connected to the first current mirror, and a second inverter is electrically connected to the second current mirror. The first and second inverters are cross-coupled.Type: GrantFiled: December 31, 2013Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao Lee, Chung-Cheng Chou
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Patent number: 9437292Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.Type: GrantFiled: February 13, 2015Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Chun Shih, Chung-Cheng Chou, Po-Hao Lee
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Publication number: 20160240251Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Inventors: YI-CHUN SHIH, CHUNG-CHENG CHOU, PO-HAO LEE
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Publication number: 20160225443Abstract: Circuits and methods for detecting write operation and limiting cell current in resistive random access memory (RRAM or ReRAM) cells are provided. RRAM cells can include a select transistor and a programmable resistor. Current can flow through the programmable resistor responsive to word line voltage VWL applied to the gate of the select transistor and a bit line voltage VBL applied to the source of the select transistor. Responsive to the current, the programmable resistor can change between relatively high and low resistances (“SET”), or between relatively low and high resistances (“RESET”). It can be desirable to accurately characterize the resistance of the programmable resistor, that is, to accurately detect write operations such as SET or RESET. Additionally, it can be undesirable for the current to exceed a certain value (“over-SET”). The present circuits and methods can facilitate detecting write operations or limiting current, or both, in an RRAM cell.Type: ApplicationFiled: January 29, 2015Publication date: August 4, 2016Inventors: CHUNG-CHENG CHOU, YI-CHUN SHIH, PO-HAO LEE
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Publication number: 20160224039Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.Type: ApplicationFiled: April 7, 2016Publication date: August 4, 2016Inventors: Chung-Cheng Chou, Po-Hao Lee
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Patent number: 9323259Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.Type: GrantFiled: November 14, 2013Date of Patent: April 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Cheng Chou, Po-Hao Lee
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Patent number: 9224464Abstract: A device includes a memory bit cell, a first current source, and a current comparator electrically connected to the memory bit cell and the first current source. A first transistor has a first terminal electrically connected to a first voltage supply node, a control terminal electrically connected to a controller, and a second terminal electrically connected to the memory bit cell and the current comparator. A sense amplifier is electrically connected to the current comparator and a reference current generator.Type: GrantFiled: February 10, 2014Date of Patent: December 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Cheng Chou, Po-Hao Lee, Jonathan Tehan Chen
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Publication number: 20150228333Abstract: A device includes a memory bit cell, a first current source, and a current comparator electrically connected to the memory bit cell and the first current source. A first transistor has a first terminal electrically connected to a first voltage supply node, a control terminal electrically connected to a controller, and a second terminal electrically connected to the memory bit cell and the current comparator. A sense amplifier is electrically connected to the current comparator and a reference current generator.Type: ApplicationFiled: February 10, 2014Publication date: August 13, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Cheng Chou, Po-Hao Lee, Jonathan Tehan Chen
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Publication number: 20150187394Abstract: A device includes first and second current mirrors electrically connected to reference and cell current sources of a memory array. A first inverter is electrically connected to the first current mirror, and a second inverter is electrically connected to the second current mirror. The first and second inverters are cross-coupled.Type: ApplicationFiled: December 31, 2013Publication date: July 2, 2015Inventors: Po-Hao Lee, Chung-Cheng Chou
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Publication number: 20150137059Abstract: The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jonathan Tehan Chen, Chung-Cheng Chou, Po-Hao Lee, Kuo-Chi Tu
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Publication number: 20150130427Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Cheng Chou, Po-Hao Lee
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Publication number: 20150069316Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.Type: ApplicationFiled: September 9, 2013Publication date: March 12, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: PO-HAO LEE, CHUNG-CHENG CHOU, WEN-TING CHU
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Publication number: 20150059362Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Cheng CHOU, Po-Hao LEE, Jonathan Tehan CHEN
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Patent number: 8509026Abstract: A word line boost circuit including a first address transfer detector, a second address transfer detector and a boost operation unit is provided. The first address transfer detector generates a first detection pulse in response to variation of a row address signal. The second address transfer detector generates a second detection pulse in response to variation of a column address signal. Moreover, the boost operation unit generates a selection voltage by using a boost voltage according to the first detection pulse, and determines whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse.Type: GrantFiled: January 10, 2012Date of Patent: August 13, 2013Assignee: eMemory Technology Inc.Inventors: Yu-Hsiung Tsai, Po-Hao Lee
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Publication number: 20130176808Abstract: A word line boost circuit including a first address transfer detector, a second address transfer detector and a boost operation unit is provided. The first address transfer detector generates a first detection pulse in response to variation of a row address signal. The second address transfer detector generates a second detection pulse in response to variation of a column address signal. Moreover, the boost operation unit generates a selection voltage by using a boost voltage according to the first detection pulse, and determines whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse.Type: ApplicationFiled: January 10, 2012Publication date: July 11, 2013Applicant: EMEMORY TECHNOLOGY INC.Inventors: Yu-Hsiung Tsai, Po-Hao Lee