Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.

Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

Abstract: A method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings in the photoresist. A first opening is near a center of the substrate and has a first width. A second opening is near an edge of the substrate and has a second width smaller than the first width. A third opening is between the first opening and the second opening and has a third width greater than the second width and smaller than the first width. The method further includes plating a conductive material into each opening. Plating the conductive material includes plating the first conductive material in the first opening at a first current density; plating the first conductive material in the second opening at a second current density greater than the first current density; and plating the conductive material in the third opening at a third current density.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Abstract: A package structure and method for forming the same are provided. The package structure includes a die structure formed over a first interconnect structure, and the die structure includes a first region and a second region. The package structure includes a dam structure formed on the first region of the die structure, and a second interconnect structure formed over the die structure and the dam structure. The package structure also includes a package layer formed between the first interconnect structure and the second interconnect structure, and the package layer is formed on the second region of the die structure to surround the dam structure.

Abstract: A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.

Abstract: A semiconductor device includes a substrate, an electrical conductor and a passivation layer. The substrate includes a first surface. The electric conductor is over the first surface of the substrate. The passivation layer is over the first surface of the substrate. The passivation layer includes a first part and a second part. In some embodiments, the first part is in contact with an edge of the electrical conductor, the second part is connected to the first part and apart from the edge of the electrical conductor, and the first part of the passivation layer has curved surface.

Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Abstract: A package includes a plurality of dies, a wall structure, an encapsulant, and a redistribution structure. The wall structure surrounds at least one of the dies. The encapsulant includes a first portion, a second portion, and a third portion. The first portion is encircled by the wall structure. The second portion encircles the wall structure. The third portion connects the first portion and the second portion. The redistribution structure is disposed on the encapsulant and is electrically connected to the dies and the wall structure.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure; a first conductive layer on the first transition layer; and a second conductive layer over the first conductive layer. The first conductive layer is substantially made of twinned copper.

Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.