Patents by Inventor Po-Hao Tsai

Po-Hao Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190043849
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Application
    Filed: October 11, 2018
    Publication date: February 7, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • SEMICONDUCTOR PACKAGE
    Publication number: 20190035738
    Abstract: The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: JING-CHENG LIN, PO-HAO TSAI, YING CHING SHIH, SZU WEI LU
  • PACKAGE STRUCTURE, INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME
    Publication number: 20190027446
    Abstract: A package structure including an integrated fan-out package and plurality of conductive terminals is provided. The integrated fan-out package includes an integrated circuit component, a plurality of conductive through vias, an insulating encapsulation having a first surface and a second surface opposite to the first surface, and a redistribution circuit structure. The insulating encapsulation laterally encapsulates the conductive through vias and the integrated circuit component. Each of conductive through vias includes a protruding portion accessibly revealed by the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit component and covers the first surface of the insulating encapsulation and the integrated circuit component.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 24, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Integrated Circuit Packages and Methods of Forming Same
    Publication number: 20190006194
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 3, 2019
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Release Film as Isolation Film in Package
    Publication number: 20190006200
    Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.
    Type: Application
    Filed: November 1, 2017
    Publication date: January 3, 2019
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Release film as isolation film in package
    Patent number: 10170341
    Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Semiconductor device method of manufacture
    Patent number: 10170451
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Chip package structure including redistribution structure and conductive shielding film
    Patent number: 10163813
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a grounding line in the dielectric structure. The grounding line includes a main portion and an end enlarged portion connected to the main portion and laterally accessible from the dielectric structure. The chip package structure includes a chip structure over the redistribution structure. The chip package structure includes a conductive shielding film disposed over the chip structure and a first sidewall of the end enlarged portion. The conductive shielding film is electrically connected to the grounding line. A thickness of the end enlarged portion increases from the main portion to the conductive shielding film.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Semiconductor package
    Patent number: 10163848
    Abstract: A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias, a polymeric cover film covering the molding compound and the die and polymeric dam structures disposed aside the connectors. The polymeric cover film and the polymeric dam structures are formed by printing.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai, Chih-Chien Pan
  • Semiconductor packages and methods of forming the same
    Patent number: 10163872
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Po-Hao Tsai
  • Method for forming chip package structure with adhesive layer
    Patent number: 10163875
    Abstract: A method for forming a chip package structure is provided. The method includes forming a chip on an adhesive layer. The chip has a front surface and a back surface opposite to the front surface. The back surface is in direct contact with the adhesive layer. A first maximum length of the adhesive layer is less than a second maximum length of the chip. The method includes forming a molding compound layer surrounding the chip and the adhesive layer. A first bottom surface of the adhesive layer is substantially coplanar with a second bottom surface of the molding compound layer. The method includes forming a redistribution structure over the chip and the molding compound layer.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin, Yi-Hang Lin
  • INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME
    Publication number: 20180366439
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Tsung-Fu Tsai, Chen-Hua Yu, Po-Hao Tsai, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai, Chen-Hsuan Tsai
  • Integrated fan-out packages and methods of forming the same
    Patent number: 10157888
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Tsung-Fu Tsai, Chen-Hua Yu, Po-Hao Tsai, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai, Chen-Hsuan Tsai
  • Integrated Fan-Out Package Structures with Recesses in Molding Compound
    Publication number: 20180350770
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 6, 2018
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices
    Publication number: 20180350756
    Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.
    Type: Application
    Filed: August 10, 2018
    Publication date: December 6, 2018
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • SEMICONDUCTOR PACKAGE STRUCTURE WITH CONDUCTIVE LINE AND METHOD FOR FORMING THE SAME
    Publication number: 20180350765
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure, and a first conductive layer on the first transition layer. The first conductive layer is substantially made of twinned copper.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hua CHANG, Jing-Cheng LIN, Po-Hao TSAI
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180342466
    Abstract: A semiconductor device package includes a substrate, a semiconductor chip, a first ring structure and a second ring structure. The substrate includes a surface. The semiconductor chip is over the surface of the substrate. The first ring structure is over the surface of the substrate. The second ring structure is over the surface of the substrate, wherein the first ring structure is between the semiconductor chip and the second ring structure.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: JING-CHENG LIN, LI-HUI CHENG, PO-HAO TSAI, JEH-YIN CHANG, LI-CHUNG KUO, HSIEN-JU TSOU, YI CHOU, YING-CHING SHIH, SZU-WEI LU
  • Semiconductor device and method
    Patent number: 10141253
    Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai
  • Semiconductor package and manufacturing method thereof
    Patent number: 10134719
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Mechanisms for forming package structure
    Patent number: 10128226
    Abstract: A package structure is provided. The package structure includes a semiconductor die and a protection layer surrounding sidewalls of the semiconductor die. The package structure also includes a conductive structure penetrating through the protection layer. The package structure further includes an interfacial layer between the protection layer and the conductive structure. The interfacial layer is made of an insulating material, and the interfacial layer is in direct contact with the protection layer. The interfacial layer extends across a back side of the semiconductor die.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jing-Cheng Lin, Po-Hao Tsai