Patents by Inventor Po-Hao Tsai

Po-Hao Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
    Patent number: 9773724
    Abstract: Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Szu Wei Lu, Jing-Cheng Lin
  • Package on Package (PoP) Bonding Structures
    Publication number: 20170271311
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Po-Hao Tsai
  • Multi-die structure and method of forming same
    Patent number: 9761566
    Abstract: A method includes forming a semiconductor device comprising a semiconductor die surrounded by a molding material, wherein a contact metal of the semiconductor device has an exposed edge, placing the semiconductor device into a tray having an inner wall and an outer wall, wherein the inner wall is underneath the semiconductor device and between an outer edge of the semiconductor device and an outer edge of bumps of the semiconductor device, depositing a metal shielding layer on the semiconductor device and the tray, wherein the metal shielding layer is in direct contact with the exposed edge of the contact metal and separating the semiconductor device from the tray.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Po-Hao Tsai, Jing-Cheng Lin, Li-Hui Cheng
  • METHOD OF CONTROLLING BUMP HEIGHT VARIATION
    Publication number: 20170229422
    Abstract: A method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings in the photoresist. A first opening is near a center of the substrate and has a first width. A second opening is near an edge of the substrate and has a second width smaller than the first width. A third opening is between the first opening and the second opening and has a third width greater than the second width and smaller than the first width. The method further includes plating a conductive material into each opening. Plating the conductive material includes plating the first conductive material in the first opening at a first current density; plating the first conductive material in the second opening at a second current density greater than the first current density; and plating the conductive material in the third opening at a third current density.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventors: Jing-Cheng LIN, Po-Hao TSAI
  • Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer
    Publication number: 20170229433
    Abstract: A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Semiconductor Device and Method
    Publication number: 20170229414
    Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Semiconductor Device and Method of Manufacture
    Publication number: 20170229434
    Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen
  • Semiconductor device and method of manufacture
    Patent number: 9728508
    Abstract: A device comprising a semiconductor device, a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Packaged semiconductor devices and packaging devices and methods
    Patent number: 9728496
    Abstract: Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Mechanisms for forming package structure
    Patent number: 9698135
    Abstract: A method for forming a package structure is provided. The method includes forming a plurality of conductive columns over a carrier substrate and forming an interfacial layer over sidewalls and tops of the conductive columns. The method also includes disposing a semiconductor die over a planar portion of the interfacial layer. The method further includes forming a molding compound to partially or completely encapsulate the semiconductor die, the conductive columns, and the interfacial layer such that the molding compound is in direct contact with the interfacial layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: July 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Semiconductor Device and Method of Manufactures
    Publication number: 20170162551
    Abstract: A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through via extends through an encapsulant. A protective layer is formed over the reflowable material. In an embodiment an opening is formed within the protective layer to expose the reflowable material. In another embodiment the protective layer is formed such that the reflowable material is extending away from the protective layer.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 8, 2017
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng
  • Package on package (PoP) bonding structures
    Patent number: 9673181
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Po-Hao Tsai
  • Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices
    Publication number: 20170154858
    Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • Mechanisms for controlling bump height variation
    Patent number: 9646942
    Abstract: The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: May 9, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Semiconductor device and method
    Patent number: 9646918
    Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME
    Publication number: 20170117261
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.
    Type: Application
    Filed: January 9, 2017
    Publication date: April 27, 2017
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Po-Hao Tsai
  • Semicondutor device and method of manufacture
    Patent number: 9633934
    Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen
  • Integrated fan-out structure with guiding trenches in buffer layer
    Patent number: 9633895
    Abstract: A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Semiconductor Device and Method of Manufacture
    Publication number: 20170084543
    Abstract: A device comprising a semiconductor device, a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks s described, defects from the marking process may be reduced or eliminated.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Pillar Design for Conductive Bump
    Publication number: 20170084571
    Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 23, 2017
    Inventors: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng