Patents by Inventor Po-Hao Tsai

Po-Hao Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20180138130
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a grounding line in the dielectric structure. The grounding line includes a main portion and an end enlarged portion connected to the main portion and laterally accessible from the dielectric structure. The chip package structure includes a chip structure over the redistribution structure. The chip package structure includes a conductive shielding film disposed over the chip structure and a first sidewall of the end enlarged portion. The conductive shielding film is electrically connected to the grounding line. A thickness of the end enlarged portion increases from the main portion to the conductive shielding film.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 17, 2018
    Inventors: Jing-Cheng LIN, Po-Hao TSAI
  • Semiconductor Device and Method
    Publication number: 20180138116
    Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.
    Type: Application
    Filed: July 3, 2017
    Publication date: May 17, 2018
    Inventors: Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai
  • Integrated fan-out package structures with recesses in molding compound
    Patent number: 9953955
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Pillar design for conductive bump
    Patent number: 9953948
    Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng
  • Through package via (TPV)
    Patent number: 9953949
    Abstract: A through package vias (TPV), a package including a plurality of the TPVs, and a method of forming the through package via are provided. Embodiments of a through package via (TPV) for a package include a build-up film layer, a metal pad disposed over the build-up film layer, a polymer ring disposed over the metal pad, and a solder feature electrically coupled with the metal pad.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Semiconductor Device and Method of Manufacture
    Publication number: 20180102345
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Application
    Filed: December 11, 2017
    Publication date: April 12, 2018
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Chip package structure with adhesive layer
    Patent number: 9929128
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure. The chip package structure includes a first chip over the redistribution structure. The first chip has a front surface and a back surface opposite to the front surface, and the front surface faces the redistribution structure. The chip package structure includes an adhesive layer on the back surface. The adhesive layer is in direct contact with the back surface, and a first maximum length of the adhesive layer is less than a second maximum length of the first chip. The chip package structure includes a molding compound layer over the redistribution structure and surrounding the first chip and the adhesive layer. A first top surface of the adhesive layer is substantially coplanar with a second top surface of the molding compound layer.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin, Yi-Hang Lin
  • Backside redistribution layer (RDL) structure
    Patent number: 9929108
    Abstract: An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Jing-Cheng Lin
  • SEMICONDUCTOR PACKAGE
    Publication number: 20180082954
    Abstract: The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 22, 2018
    Inventors: JING-CHENG LIN, PO-HAO TSAI, YING CHING SHIH, SZU WEI LU
  • Interconnect structure for package-on-package devices and a method of fabricating
    Patent number: 9922903
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages
    Publication number: 20180012830
    Abstract: Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 11, 2018
    Inventors: I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Szu-Wei Lu, Jing-Cheng Lin
  • SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180006005
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Application
    Filed: August 12, 2016
    Publication date: January 4, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A PACKAGED SEMICONDUCTOR DEVICE
    Publication number: 20170373016
    Abstract: In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive bump, a second package structure, a sealing material, and an electromagnetic interference (EMI) shielding layer. The first package structure has a first cut edge. The outer conductive bump is disposed on the first package structure and has a second cut edge. The second package structure is jointed onto the first package structure. The sealing material is disposed on the first package structure, surrounds the second package structure, and covers the outer conductive bump. The sealing material has a third cut edge. The EMI shielding layer contacts the first cut edge, the second cut edge and the third cut edge. The EMI shielding layer is electrically connected with the outer conductive bump.
    Type: Application
    Filed: August 12, 2016
    Publication date: December 28, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Multi-Die Structure and Method for Forming Same
    Publication number: 20170373048
    Abstract: A device includes a semiconductor structure comprising a top package stacked on a bottom package, wherein the bottom package comprises a plurality of bottom package bumps on a bottom surface of the bottom package, a front side contact metal, a molding compound layer and a backside contact metal, and wherein the front side contact metal is between the plurality of bottom package bumps and the molding compound layer and a metal shielding layer on a top surface, sidewalls of the semiconductor structure and portions of a bottom surface of the bottom package, wherein the metal shielding layer is in direct contact with an edge of at least one of the front side contact metal and the backside contact metal.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Inventors: Chen-Hua Yu, Po-Hao Tsai, Jing-Cheng Lin, Li-Hui Cheng
  • Semiconductor device and method of manufacture
    Patent number: 9842826
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Semiconductor Device and Method of Manufacture
    Publication number: 20170338185
    Abstract: A device comprising a semiconductor device, a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Application
    Filed: August 7, 2017
    Publication date: November 23, 2017
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Packaged Semiconductor Devices and Packaging Devices and Methods
    Publication number: 20170338177
    Abstract: Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound.
    Type: Application
    Filed: August 7, 2017
    Publication date: November 23, 2017
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Semiconductor package manufacturing method
    Patent number: 9818697
    Abstract: The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Ying Ching Shih, Szu Wei Lu
  • Integrated fan-out structure with openings in buffer layer
    Patent number: 9799581
    Abstract: A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu Sen Chiu, Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • MECHANISMS FOR FORMING PACKAGE STRUCTURE
    Publication number: 20170301663
    Abstract: A package structure is provided. The package structure includes a semiconductor die and a protection layer surrounding sidewalls of the semiconductor die. The package structure also includes a conductive structure penetrating through the protection layer. The package structure further includes an interfacial layer between the protection layer and the conductive structure. The interfacial layer is made of an insulating material, and the interfacial layer is in direct contact with the protection layer. The interfacial layer extends across a back side of the semiconductor die.
    Type: Application
    Filed: July 3, 2017
    Publication date: October 19, 2017
    Inventors: Jing-Cheng LIN, Po-Hao TSAI