Abstract: A self-protection circuitry is configured to receive a first power source. The self-protection circuitry includes a first transistor circuit, a first switch circuit, and a control circuit. The first transistor circuit includes a first input terminal, a first output terminal, and a first control terminal. The first input terminal is configured to receive the first power source. The first output terminal is electrically connected to a ground terminal. The first switch circuit is electrically connected to the first input terminal and the ground terminal. The control circuit is electrically connected to the first switch circuit, and is configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit to be turned on, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit to be turned off.

Abstract: A self-protection circuitry is configured to receive a first power source. The self-protection circuitry includes a first transistor circuit, a first switch circuit, and a control circuit. The first transistor circuit includes a first input terminal, a first output terminal, and a first control terminal. The first output terminal is electrically connected to a ground terminal, and the first input terminal is configured to receive the first power source. The first switch circuit is electrically connected to the first control terminal and the first input terminal. The control circuit is electrically connected to the first switch circuit, and is configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit to be 10 conducted, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit to be cut off.

Abstract: A TCAM comprises multiple first search lines, multiple second search lines, multiple memory cell strings, and one or more current sensing units coupled to the plurality of memory cell strings. Each memory cell string comprises multiple memory cells. Each memory cell string comprises at least four transistors serially connected as a NAND memory string, and two transistors of the at least four transistors form each memory cell. One, of the two transistors in each memory cell, coupled to one of the first search lines is a first transistor, and the other one, of the two transistors in each memory cell, coupled to one of the second search lines is a second transistor. The multiple first search lines are arranged consecutively, and the multiple second search lines are arranged consecutively.

Abstract: The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

Abstract: A high-level architecture for 3D-NAND based in-memory search provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. A search word is presented to a 3D-NAND memory along a direction of a bit line of the 3D-NAND memory. Each character of the word comprises a number of digits. Each digit is matched against respective layers of the 3D-NAND memory. Each digit is usable to represent one of a plurality of levels according to a selected encoding. Optionally, various lengths of words are accommodated via serial and/or parallel operations of one or more 3D-NAND memories.

Abstract: An operating method of a memory system is disclosed herein. The operating method includes: inputting tracking data to a tracking array; generating tracking logic values by tracking cell columns of the tracking array according to the tracking data; counting the tracking logic values to generate a summation value; adjusting a sensing time of a sensing device according to the summation value; performing a computing operation by a computing array to generate computing signals; and sensing the computing signals by the sensing device according to the adjusted sensing time.

Abstract: A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.

Abstract: A non-volatile 3D memory search architecture provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. The architecture uses two word lines per unit of information of the searches and two memory devices per unit of stored feature to search against. The architecture uses respective bit lines of the non-volatile 3D memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the non-volatile 3D memory array are usable to store respective data values, e.g., corresponding to elements to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. The architecture has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

Abstract: A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material on a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An insulating structure is arranged over and along opposing outermost sidewalls of the top electrode. The bottom electrode laterally extends to different non-zero distances past opposing outermost sidewalls of the insulating structure.

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

Abstract: A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.

Abstract: An in memory searching device, including multiple first memory cell strings, a controller, and a sensing circuit, is provided. The first memory cell strings are commonly coupled to a first common bit line. Each of the first memory strings includes multiple first data storage layers. The first data storage layers respectively include multiple first memory cell pairs. The first memory cell pairs are respectively coupled to multiple first word line pairs. The controller selects at least one of the first data storage layers to be at least one selected data storage layer, and provides search data to at least one selected word line pair corresponding to the at least one selected data storage layer. The sensing circuit senses a current on the first common bit line to generate a search result.

Abstract: A memory cell and a memory device are provided. The memory cell comprises: a write transistor; and a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data; wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable.

Abstract: A memory device and an in-memory search method thereof are provided. The in-memory search method includes: providing, in a first stage, a first voltage or a second voltage to a word line of at least one target memory cell according to a logical status of searched data, and reading a first current; providing, in a second stage, a third voltage or a fourth voltage to the word line of the at least one target memory cell according to the logical status of the searched data, and reading a second current; and obtaining a search result according to a difference between the second current and the first current.

Abstract: An in-dynamic memory search device and an operation method thereof are provided. The in-dynamic memory search device includes at least one word line, at least two bit lines, at least one match line, at least one unit cell, at least two search lines, at least one pre-charge unit and at least one sense unit. The unit cell includes two storage elements and two search transistors. Each of the storage elements includes a write transistor and a read transistor. The write transistor is connected to the word line and one of the bit lines. The read transistor is connected to the write transistor and the match line. The search transistors are respectively connected to the read transistors. The search lines are respectively connected to the search transistors. The pre-charge unit is connected to the match line. The sense unit is connected to the match line.

Abstract: A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.

Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.