Patents by Inventor Po-Lin Chen

Po-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220381392
    Abstract: A supporting device is provided and includes: a base; an upright column disposed on the base; a lifting module disposed on the upright column; a constant force arm unit including: a first rotating member rotatably disposed on the upright column and defining a constant first effective force arm; and a first wire wound on the first rotating member; a variable force arm unit including: a second rotating member linked with the first rotating member and defining a variable second effective force arm; and a second wire wound on the second rotating member; and an elastic force module connected to the first wire; where the torques respectively generated in the first wire and the second wire are balanced with each other.
    Type: Application
    Filed: January 27, 2022
    Publication date: December 1, 2022
    Inventors: Chun-Hao Huang, Chien-Wei Cheng, Yaw-Lin Chen, Po-Chun Chiu, Chien-Cheng Yeh
  • Publication number: 20220386440
    Abstract: A method for generating EUV light includes providing a laser beam having a Gaussian distribution. This laser beam can be then modified from a Gaussian distribution to a ring-like distribution. The modified laser beam is provided through an aperture in a collector and interfaces with a moving droplet target, which generates an extreme ultraviolet (EUV) wavelength light. The generated EUV wavelength light is provided to the collector away from the aperture. In some embodiments, a mask element may also be used to modify the laser beam to a shape.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Chun-Lin Louis CHANG, Jen-Hao YEH, Tzung-Chi FU, Bo-Tsun LIU, Lin-Jui CHEN, Po-Chung CHENG
  • Publication number: 20220376086
    Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.
    Type: Application
    Filed: August 5, 2022
    Publication date: November 24, 2022
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Chia-Ling Yeh, Ching Yu Chen
  • Publication number: 20220375875
    Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 24, 2022
    Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
  • Patent number: 11508817
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20220362780
    Abstract: An integrated nucleic acid processing apparatus includes a first operation area, a second operation area and a separation wall. The first operation area includes multiple carrying boards for placing objects and reagents for processing nucleic acids in samples, and multiple operation modules for performing operations of nucleic acid processing. The second operation area includes two extraction regions for respectively performing nucleic acid extractions. The separation wall separates the first operation area from the second operation area and includes two openable door sheets spatially corresponding to the two extraction regions. Nucleic acid extraction plates can be moved from the first operation area to the second operation area by means of the carrying boards as the two openable door sheets are opened, and be isolated in the second operation area for performing nucleic acid extractions as the two openable door sheets are closed.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 17, 2022
    Inventors: Jing Geng, Yang Liu, Song-Bin Huang, Chien-Ting Liu, Yen-You Chen, Po-Lin Chou, Chih-Yang Chen
  • Publication number: 20220367638
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20220359681
    Abstract: In some embodiments, the present disclosure relates to a method of forming a transistor device. The method includes forming a source contact over a substrate, forming a drain contact over the substrate, and forming a gate contact material over the substrate. The gate contact material is patterned to define a gate structure that wraps around the source contact along a continuous and unbroken path.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Aurelien Gauthier Brun, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Yun-Hsiang Wang
  • Publication number: 20220361311
    Abstract: A method for monitoring a shock wave in an extreme ultraviolet light source includes irradiating a target droplet in the extreme ultraviolet light source apparatus of an extreme ultraviolet lithography tool with ionizing radiation to generate a plasma and to detect a shock wave generated by the plasma. One or more operating parameters of the extreme ultraviolet light source is adjusted based on the detected shock wave.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Yen-Shuo SU, Jen-Hao YEH, Jhan-Hong YEH, Ting-Ya CHENG, Yee-Shian Henry TONG, Chun-Lin CHANG, Han-Lung CHANG, Li-Jui CHEN, Po-Chung CHENG
  • Publication number: 20220359346
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen
  • Publication number: 20220351923
    Abstract: A key module includes a base plate, a circuit layer and a lifting mechanism. The circuit layer is disposed on the base plate. The lifting mechanism is pivotally connected with the base plate relative to the circuit layer, and the lifting mechanism has an abutment element. The abutment element could interfere with the circuit layer to reduce the noise generated by the key module during operation.
    Type: Application
    Filed: July 12, 2022
    Publication date: November 3, 2022
    Inventors: Chun-Lin CHEN, Jui-Yu WU, Po-Hsiang YU
  • Publication number: 20220338333
    Abstract: An extreme ultra violet (EUV) radiation source apparatus includes a collector mirror, a target droplet generator for generating a tin (Sn) droplet, a rotatable debris collection device, one or more coils for generating an inductively coupled plasma (ICP), a gas inlet for providing a source gas for the ICP, and a chamber enclosing at least the collector mirror and the rotatable debris collection device. The gas inlet and the one or more coils are configured such that the ICP is spaced apart from the collector mirror.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Yen-Shuo SU, Chun-Lin CHANG, Han-Lung CHANG, Li-Jui CHEN, Po-Chung CHENG
  • Patent number: 11476404
    Abstract: An ultrasonic sensing device includes a housing, a piezoelectric assembly, a board and a plurality of fixing members. The housing includes a bottom wall, a top wall and a surrounding side wall connected between the top wall and the bottom wall. The piezoelectric assembly includes an encapsulating body and a piezoelectric sheet, wherein at least a portion of the piezoelectric sheet is enclosed by the encapsulating body and has a sensing surface exposed to the encapsulating body and facing the bottom wall. The board is disposed on the top wall of the housing and has a pressing surface facing the encapsulating body and the top wall. The plurality of fixing members is configured to fix the board to the top wall of the housing to press the board to the encapsulating body of the piezoelectric assembly, thereby pressing the sensing surface of the piezoelectric sheet to the bottom wall.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: October 18, 2022
    Assignee: Qian Jun Technology Ltd.
    Inventors: Chi-Shen Lee, Yu-Yen Fu, Po-Chun Yeh, Dong-Fu Chen, Chih-Wen Cheng, Chi-Lin Huang, Yu-Ping Yen
  • Publication number: 20220328561
    Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.
    Type: Application
    Filed: August 20, 2021
    Publication date: October 13, 2022
    Inventors: Jui-Lin CHEN, Chenchen Jacob WANG, Hsin-Wen SU, Ping-Wei WANG, Yuan-Hao CHANG, Po-Sheng LU, Shih-Hao LIN
  • Patent number: 11468863
    Abstract: A gate driving circuit includes a bootstrapping circuit, a pre-charge circuit, and an output control circuit. The bootstrapping circuit is composed of a bootstrapping capacitor and a transistor. A first terminal of the bootstrapping capacitor has a first voltage during a first duration. The pre-charge circuit is connected to the first terminal of the bootstrapping capacitor. The pre-charge circuit boosts the first terminal of the bootstrapping capacitor from the first voltage to a second voltage during a second duration. The bootstrapping circuit boosts the first terminal of the bootstrapping capacitor from the second voltage to a third voltage during a third duration. The output control circuit is connected to the first terminal of the bootstrapping capacitor. The output control circuit boosts the first terminal of the bootstrapping capacitor from the third voltage to a fourth voltage during a fourth duration.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 11, 2022
    Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., Interface Optoelectronics (Wuxi) Co., Ltd., General Interface Solution Limited
    Inventors: Po-Lun Chen, Chun-Ta Chen, Chih-Lin Liao, Fu-Cheng Wei, Po-Tsun Liu, Guang-Ting Zheng, Ping-Hung Hsieh
  • Patent number: 11460947
    Abstract: A touch screen includes a touch panel including a plurality of touch blocks, and a knob, being touch-sensitive and rotatable, disposed on top of the touch panel. An area of the touch panel not covered with the knob is defined as a first area, an area of the touch panel covered with the knob is defined as a second area, and touch blocks belonging to both the first area and the second area are defined as overlapped blocks. Sense signals associated with the overlapped blocks are de-emphasized.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: October 4, 2022
    Assignee: Himax Technologies Limited
    Inventors: Chun-Jen Su, Chun-Kai Chuang, Cheng-Hung Tsai, Po-Hsuan Huang, Li-Lin Liu, Heng-Xiao Chen
  • Patent number: 11452197
    Abstract: A method for monitoring a shock wave in an extreme ultraviolet light source includes irradiating a target droplet in the extreme ultraviolet light source apparatus of an extreme ultraviolet lithography tool with ionizing radiation to generate a plasma and to detect a shock wave generated by the plasma. One or more operating parameters of the extreme ultraviolet light source is adjusted based on the detected shock wave.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Shuo Su, Jen-Hao Yeh, Jhan-Hong Yeh, Ting-Ya Cheng, Yee-Shian Henry Tong, Chun-Lin Chang, Han-Lung Chang, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 11439871
    Abstract: A system for determining an assessment of at least one exercise performed by a user is described. The system includes an input device, and a computing device. The input device is configured to monitor at least one exercise performed by a user. The computing device includes processors and a memory. The memory is coupled to the processors and stores program instructions that when executed by the processors cause the processors to: (1) generate a user interface displaying a content; (2) provide an instruction associated with the at least one exercise; (3) determine an indication of movement associated with the at least one exercise; (4) in response to a determination of the indication of movement, determine an assessment of the at least one exercise; and (5) in response to a determination of the assessment of the at least one exercise, perform an operation.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 13, 2022
    Assignee: Conzian Ltd.
    Inventors: Yan-Fu Liu, Po-Jui Huang, Liang-Kai Wang, Chung-Hsien Wu, Jian-Lin Chen
  • Publication number: 20220283981
    Abstract: A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 8, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Po-Lin Wei, Ching-Lung Chen
  • Publication number: 20220271088
    Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.
    Type: Application
    Filed: March 15, 2021
    Publication date: August 25, 2022
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Kun-I Chou, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Hung-Yueh Chen