Patents by Inventor Po Tang
Po Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150143304Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hui Chih, Wen-Li Cheng, Yu-Po Tang, Ping-Chieh Wu, Chia-Ping Chiang, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 9026957Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.Type: GrantFiled: February 25, 2014Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
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Publication number: 20150085356Abstract: A microscope apparatus includes an electromagnetic wave source configured to generate an illuminating electromagnetic wave, a first beam splitter configured to split the illuminating electromagnetic wave into a first component along a first path and a second component along a second path, a movable reflector module configured to adjust a portion of the second path, and a second beam splitter configured to recombine the first component and the second component. An observing device is configured to receive the recombined first component and second component and the microscope apparatus is configured acquire a phase image from the observing device based on positioning of the movable reflector module and representative of an electric field distribution near an object located along the first path between the first beam splitter and the second beam splitter.Type: ApplicationFiled: December 3, 2014Publication date: March 26, 2015Inventors: Fu-Sheng CHU, Chih-Shiang CHOU, Yu-Po TANG, Yan-Ying HE
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Patent number: 8928973Abstract: A microscope apparatus includes a condenser lens to make an illuminating electromagnetic wave relatively homogeneous, a first beam splitter splitting the illuminating electromagnetic wave after the condenser lens, a movable reflector module, a second beam splitter, an objective lens to project the illuminating electromagnetic wave propagating after an object to be observed toward an observing device. The object is loaded between the first beam splitter and the second beam splitter. The microscope apparatus is configured to split the illuminating electromagnetic wave into two paths at the first beam splitter. A first path goes through the first and the second beam splitters, and a second path goes through the movable reflector module to rejoin the first path at the second beam splitter. The microscope apparatus is configured acquire phase images with interferences of the electromagnetic wave from the two paths with at least two distance settings of the movable reflector module.Type: GrantFiled: December 16, 2011Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Sheng Chu, Chih-Shiang Chou, Yu-Po Tang, Yan-Ying He
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Publication number: 20140322910Abstract: The present disclosure provides a method for forming a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.Type: ApplicationFiled: July 15, 2014Publication date: October 30, 2014Inventors: Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh, Ru-Gun Liu
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Patent number: 8806392Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.Type: GrantFiled: December 3, 2012Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Tzu-Chin Lin, Jen-Chieh Lo, Yu-Po Tang, Tsong-Hua Ou
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Patent number: 8779592Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.Type: GrantFiled: May 1, 2012Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh, Ru-Gun Liu
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Publication number: 20140170537Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.Type: ApplicationFiled: February 25, 2014Publication date: June 19, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
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Publication number: 20140157212Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Tzu-Chin Lin, Jen-Chieh Lo, Yu-Po Tang, Tsong-Hua Ou
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Patent number: 8745550Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.Type: GrantFiled: July 9, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nian-Fuh Cheng, Yu-Po Tang, Chien-Fu Lee, Sheng-Wen Lin, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20140109026Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.Type: ApplicationFiled: December 30, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Feng-Ju Chang, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8673520Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.Type: GrantFiled: March 11, 2011Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
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Patent number: 8631360Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.Type: GrantFiled: April 17, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Feng-Ju Chang, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20140013287Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.Type: ApplicationFiled: July 9, 2012Publication date: January 9, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nian-Fuh Cheng, Yu-Po Tang, Chien-Fu Lee, Sheng-Wen Lin, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20130292836Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.Type: ApplicationFiled: May 1, 2012Publication date: November 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh, Ru-Gun Liu
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Patent number: 8572520Abstract: Integrated circuit (IC) methods for optical proximity correction (OPC) modeling and mask repair are described. The methods include use of an optical model that generates a simulated aerial image from an actual aerial image obtained in an optical microscope system. In the OPC modeling methods, OPC according to stage modeling is simulated, and OPC features may be added to a design layout according to the simulating OPC. In the mask repair methods, inverse image rendering is performed on the actual aerial image and diffraction image by applying an optical model that divides an incoherent exposure source into a plurality of coherent sources.Type: GrantFiled: March 1, 2012Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Shiang Chou, Ya-Ting Chang, Fu-Sheng Chu, Yu-Po Tang
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Publication number: 20130275926Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.Type: ApplicationFiled: April 17, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chun Wang, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Feng-Ju Chang, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20130246981Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.Type: ApplicationFiled: March 14, 2012Publication date: September 19, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ping Chiang, Tsong-Hua Ou, Yu-Po Tang, Ming-Hui Chih, Wen-Li Cheng, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20130232454Abstract: Integrated circuit (IC) methods for optical proximity correction (OPC) modeling and mask repair are described. The methods include use of an optical model that generates a simulated aerial image from an actual aerial image obtained in an optical microscope system. In the OPC modeling methods, OPC according to stage modeling is simulated, and OPC features may be added to a design layout according to the simulating OPC. In the mask repair methods, inverse image rendering is performed on the actual aerial image and diffraction image by applying an optical model that divides an incoherent exposure source into a plurality of coherent sources.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.Inventors: Chih-Shiang Chou, Ya-Ting Chang, Fu-Sheng Chu, Yu-Po Tang
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Patent number: 8527916Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.Type: GrantFiled: March 14, 2012Date of Patent: September 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ping Chiang, Tsong-Hua Ou, Yu-Po Tang, Ming-Hui Chih, Wen-Li Cheng, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu