Patents by Inventor Po-Tsun Liu
Po-Tsun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9972719Abstract: A laminate structure of a thin film transistor includes a thin film transistor array and a passivation layer. The thin film transistor array includes a gate, a channel layer formed on the gate, a gate insulating layer formed between the gate and the channel layer, and a source and a drain formed on both sides of the channel layer. The passivation layer is formed on the thin film transistor array, and the passivation layer has at least one contact hole exposing the source or the drain, wherein the passivation layer is an oxazole-containing photosensitive polyimide (PSPI) resin.Type: GrantFiled: March 1, 2017Date of Patent: May 15, 2018Assignee: Microcosm Technology Co., Ltd.Inventors: Po-Tsun Liu, Sung-Wei Hung, Bo-Hung Lai
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Publication number: 20180122953Abstract: A laminate structure of a thin film transistor includes a thin film transistor array and a passivation layer. The thin film transistor array includes a gate, a channel layer formed on the gate, a gate insulating layer forming between the gate and the channel layer, and a source and a drain forming on both sides of the channel layer. The passivation layer is formed on the thin film transistor array, and the passivation layer has at least one contact hole exposing the source or the drain, wherein the passivation layer is an oxazole-containing photosensitive polyimide (PSPI) resin.Type: ApplicationFiled: March 1, 2017Publication date: May 3, 2018Applicant: Microcosm Technology Co., Ltd.Inventors: Po-Tsun Liu, Sung-Wei Hung, Bo-Hung Lai
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Publication number: 20180061350Abstract: A gate driving circuit is provided. The gate driving circuit includes multistage driving modules, where an Nth stage driving module includes a setting circuit, a first driving circuit, an isolating switch circuit, a second driving circuit and an anti-noise circuit. The setting circuit generates a first precharge signal according to a gate driving signal of an (N?2)th scan line or a start signal. The isolating switch circuit coupled between the first driving circuit and the second driving circuit provides a second precharge signal, so as to effectively avoid a flickering problem of a display image caused by a surge of the gate driving signal due to a coupling effect of a parasitic capacitance of the transistor and a bootstrap capacitor, and meanwhile the bootstrap capacitor is not used, so as to effectively reduce a bezel area.Type: ApplicationFiled: October 27, 2016Publication date: March 1, 2018Applicants: Chunghwa Picture Tubes, LTD., National Chiao Tung UniversityInventors: Wei-Lien Sung, Han-Lung Liu, Wen-Chuan Wang, Chi-Liang Kuo, Yuan-Hao Chang, Wen-Che Wang, Po-Tsun Liu, Guang-Ting Zheng, Yu-Fan Tu
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Publication number: 20170309238Abstract: A display panel includes a substrate, and a pixel array and a gate driving circuit. The gate driving circuit provides gate driving signals to the pixel array, and includes shift registers, wherein each shift register includes a voltage providing unit, a first driving transistor, a voltage transmitting unit and a second driving transistor. The voltage providing unit receives a setting signal and a system high voltage to provide a first terminal voltage. The first driving transistor receives a first clock signal and the first terminal voltage to provide a first gate driving signal. The voltage transmitting unit receives the first gate driving signal to provide a second terminal voltage. The second driving transistor receives a second clock signal and the second terminal voltage to provide a second gate driving signal. Therefore, the influence caused by large difference of driving capabilities of the first and the second driving transistor is avoided.Type: ApplicationFiled: May 9, 2016Publication date: October 26, 2017Inventors: Wei-Lien Sung, Han-Lung Liu, Wen-Chuan Wang, Shao-Lun Chang, Shih-Chieh Lin, Po-Tsun Liu, Guang-Ting Zheng, Shao-Huan Hung
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Patent number: 9792869Abstract: A display panel includes a substrate, and a pixel array and a gate driving circuit. The gate driving circuit provides gate driving signals to the pixel array, and includes shift registers, wherein each shift register includes a voltage providing unit, a first driving transistor, a voltage transmitting unit and a second driving transistor. The voltage providing unit receives a setting signal and a system high voltage to provide a first terminal voltage. The first driving transistor receives a first clock signal and the first terminal voltage to provide a first gate driving signal. The voltage transmitting unit receives the first gate driving signal to provide a second terminal voltage. The second driving transistor receives a second clock signal and the second terminal voltage to provide a second gate driving signal. Therefore, the influence caused by large difference of driving capabilities of the first and the second driving transistor is avoided.Type: GrantFiled: May 9, 2016Date of Patent: October 17, 2017Assignees: Chunghwa Picture Tubes, LTD., National Chiao Tung UniversityInventors: Wei-Lien Sung, Han-Lung Liu, Wen-Chuan Wang, Shao-Lun Chang, Shih-Chieh Lin, Po-Tsun Liu, Guang-Ting Zheng, Shao-Huan Hung
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Publication number: 20170053595Abstract: A pixel circuit includes first to third switches, a transistor, a light emitting diode, and first and second capacitors. The first switch has its control end coupled to a first scan line and its first end for receiving a data signal. The second switch has its control end coupled to a second scan line and its third end for receiving a power supply voltage. The transistor has its control end coupled to the second end and its fifth end coupled to the fourth end. The third switch has its control end coupled to a third scan line and its eighth end coupled to the sixth end. the light emitting diode has its anode and cathode coupled to the eighth end and a reference voltage level, respectively. The first and second capacitors are coupled between the second end and seventh end and between the seventh end and reference voltage level, respectively.Type: ApplicationFiled: August 17, 2015Publication date: February 23, 2017Inventors: PO-TSUN LIU, GUANG-TING ZHENG, CHENG-YU TSAI, HSING-HUNG HSIEH, CHUNG-CHIN HSIAO
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Publication number: 20160344220Abstract: The present invention provides a temperature sensing circuit, which comprises a switching circuit, a charging circuit, and a judging circuit. The switching circuit receives a supply voltage for generating a switching signal. The charging circuit is coupled to the switching circuit and receives the supply voltage. The switching signal controls the charging circuit for generating a voltage signal according to the supply voltage. The judging circuit is coupled to the charging circuit for generating a judging signal according to the level of the voltage signal. The levels of the switching signal and the voltage signal are related to a temperature state; and the judging signal represents the temperature state. The temperature sensing circuit can be applied to the driving circuit of a display panel for detecting the temperature state. Hence, the level of the driving signal of the driving circuit can be adjusted for improving the image quality.Type: ApplicationFiled: July 26, 2013Publication date: November 24, 2016Applicants: NATIONAL CHIAO TUNG UNIVERSITY, GIANTPLUS TECHNOLOGY CO., LTD.Inventors: PO-TSUN LIU, LI-WEI CHU, GUANG-TING ZHENG, YI-CHUN KUO, CHUN-YEN CHEN, KU-HUANG LAI
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Patent number: 9312484Abstract: A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO).Type: GrantFiled: November 13, 2015Date of Patent: April 12, 2016Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Po-Tsun Liu, Yang-Shun Fan, Chun-Ching Chen
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Publication number: 20160072063Abstract: A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO).Type: ApplicationFiled: November 13, 2015Publication date: March 10, 2016Inventors: Po-Tsun LIU, Yang-Shun FAN, Chun-Ching CHEN
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Patent number: 9219099Abstract: A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO).Type: GrantFiled: December 4, 2014Date of Patent: December 22, 2015Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Po-Tsun Liu, Yang-Shun Fan, Chun-Ching Chen
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Patent number: 9111811Abstract: The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack.Type: GrantFiled: August 8, 2013Date of Patent: August 18, 2015Assignee: National Chiao Tung UniversityInventors: Po-Tsun Liu, Li-Wei Chu, Ming-Dou Ker
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Patent number: 9093427Abstract: A method for fabricating a semiconductor device is disclosed in the present invention. The abovementioned method comprises the following steps. Firstly, a gate is formed on a substrate. A gate insulating layer is then formed on the gate, and further an active layer is disposed on the gate insulating layer, wherein the active layer is composed of a microwave absorbing material. Source/drain is defined on the active layer to form the semiconductor device, and a microwave annealing process is finally performed thereon.Type: GrantFiled: June 19, 2013Date of Patent: July 28, 2015Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Po-Tsun Liu, Li-Feng Teng, Yuan-Jou Lo, Yao-Jen Lee
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Patent number: 8975164Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.Type: GrantFiled: May 30, 2013Date of Patent: March 10, 2015Assignee: National Chiao Tung UniversityInventors: Po-Tsun Liu, Wei-Ya Wang, Li-Feng Teng
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Patent number: 8969868Abstract: A thin film transistor comprises a transparent substrate, a gate is disposed on the transparent substrate, a gate insulator is disposed on the gate and the transparent substrate, an active layer is disposed on the gate insulator, an electrode layer is electrically connected the active layer and the portion of the active layer is exposed, and an ultraviolet light absorbing layer is disposed on the electrode layer. By using the advantage of the ultraviolet light absorbing layer with the range of visible light transmittance and with the component protection, preventing the optical characteristics of the thin film transistor from the outside moisture is achieved, and by adjusting the parameters in the thin film deposition process to change its conductivity.Type: GrantFiled: August 26, 2013Date of Patent: March 3, 2015Assignee: National Chiao Tung UniversityInventors: Han-Ping D. Shieh, Po-Tsun Liu, Yun-Chu Tsai, Min-Yen Tsai, Li-Feng Teng
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Patent number: 8963900Abstract: The invention provides a bidirectional scanning driving circuit, which comprises N stages of driving modules. Driving module comprises an output unit, a forward input unit, and a reverse input unit. For the n-th stage driving module, the forward input unit receives a first input voltage and a front forward scan signal of any of the driving modules lower than or equal to (n?2)th stage for charging or discharging a control node of the output unit. The reverse input unit receives a second input voltage and a back reverse scan signal of any of the driving modules higher than or equal to (n+2)th stage for charging or discharging the control node of the output unit. When the forward input unit is charging the output unit, the output unit outputs a forward scan signal; when the reverse input unit is charging the output unit, the output unit outputs a reverse scan signal.Type: GrantFiled: March 15, 2013Date of Patent: February 24, 2015Assignees: Giantplus Technology Co., Ltd., National Chiao Tung UniversityInventors: Po-Tsun Liu, Li-Wei Chu, Guang-Ting Zheng, Chun-Yen Chen, Yi-Chun Kuo, Kai-Ju Chou, Che-Yao Wu, Po-Chun Huang, Ku-Huang Lai
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Publication number: 20140361287Abstract: A thin film transistor comprises a transparent substrate, a gate is disposed on the transparent substrate, a gate insulator is disposed on the gate and the transparent substrate, an active layer is disposed on the gate insulator, an electrode layer is electrically connected the active layer and the portion of the active layer is exposed, and an ultraviolet light absorbing layer is disposed on the electrode layer. By using the advantage of the ultraviolet light absorbing layer with the range of visible light transmittance and with the component protection, preventing the optical characteristics of the thin film transistor from the outside moisture is achieved, and by adjusting the parameters in the thin film deposition process to change its conductivity.Type: ApplicationFiled: August 26, 2013Publication date: December 11, 2014Applicant: National Chiao Tung UniversityInventors: Han-Ping D. SHIEH, Po-Tsun LIU, Yun-Chu TSAI, Min-Yen TSAI, Li-Feng TENG
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Publication number: 20140287561Abstract: A method for fabricating a semiconductor device is disclosed in the present invention. The abovementioned method comprises the following steps. Firstly, a gate is formed on a substrate. A gate insulating layer is then formed on the gate, and further an active layer is disposed on the gate insulating layer, wherein the active layer is composed of a microwave absorbing material. Source/drain is defined on the active layer to form the semiconductor device, and a microwave annealing process is finally performed thereon.Type: ApplicationFiled: June 19, 2013Publication date: September 25, 2014Applicant: National Chiao Tung UniversityInventors: Po-Tsun LIU, Li-Feng TENG, Yuan-Jou LO, Yao-Jen LEE
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Patent number: 8842462Abstract: A resistive random access memory (RRAM) device and operating method are disclosed herein. The RRAM device includes at least one RRAM cell and a control circuit. The RRAM cell includes a bottom electrode, an amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) layer, a Ti layer and a top electrode. The a-IGZO layer is disposed on the bottom layer. The Ti layer is disposed on the a-IGZO layer. The top electrode is disposed on the Ti layer. The control circuit is configured to provide at least one electrical signal to the RRAM cell, so as to change the resistance value of the RRAM cell.Type: GrantFiled: January 30, 2013Date of Patent: September 23, 2014Assignee: National Chiao Tung UniversityInventors: Po-Tsun Liu, Ching-Hui Hsu, Yang-Shun Fan
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Publication number: 20140193964Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.Type: ApplicationFiled: May 30, 2013Publication date: July 10, 2014Applicant: National Chiao Tung UniversityInventors: Po-Tsun LIU, Wei-Ya WANG, Li-Feng TENG
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Publication number: 20140133213Abstract: A resistive random access memory (RRAM) device and operating method are disclosed herein. The RRAM device includes at least one RRAM cell and a control circuit. The RRAM cell includes a bottom electrode, an amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) layer, a Ti layer and a top electrode. The a-IGZO layer is disposed on the bottom layer. The Ti layer is disposed on the a-IGZO layer. The top electrode is disposed on the Ti layer. The control circuit is configured to provide at least one electrical signal to the RRAM cell, so as to change the resistance value of the RRAM cell.Type: ApplicationFiled: January 30, 2013Publication date: May 15, 2014Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Po-Tsun LIU, Ching-Hui HSU, Yang-Shun FAN