Abstract: A method for removing germanium suboxide between a germanium (Ge) substrate and a dielectric layer made of metal oxide includes causing a supercritical fluid composition that includes a supercritical carbon dioxide fluid and an oxidant to diffuse into the germanium suboxide such that metal residues in the dielectric layer, the germanium suboxide and the oxidant are subjected to a redox reaction so as to reduce the germanium suboxide into germanium.

Abstract: A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells.

Abstract: The invention provides a bidirectional scanning driving circuit, which comprises N stages of driving modules. Driving module comprises an output unit, a forward input unit, and a reverse input unit. For the n-th stage driving module, the forward input unit receives a first input voltage and a front forward scan signal of any of the driving modules lower than or equal to (n?2)th stage for charging or discharging a control node of the output unit. The reverse input unit receives a second input voltage and a back reverse scan signal of any of the driving modules higher than or equal to (n+2)th stage for charging or discharging the control node of the output unit. When the forward input unit is charging the output unit, the output unit outputs a forward scan signal; when the reverse input unit is charging the output unit, the output unit outputs a reverse scan signal.

Abstract: A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells.

Abstract: A semiconductor structure and a fabricating method thereof are provided. The fabricating method includes forming a gate, a source, and a drain on a substrate and forming an oxide semiconductor material between the gate and the source and drain. The oxide semiconductor material is formed by performing a deposition process, and nitrogen gas is introduced before the deposition process is completely performed, so as to form oxide semiconductor nitride on the oxide semiconductor material.

Abstract: The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack.

Abstract: The present invention relates to a high gain complementary inverter with ambipolar thin film transistors and fabrication thereof, comprising: a gate layer, a silica layer, a first active layer, a first source, a first drain, a second active layer, a second source and a second drain for fabrication cost and complexity reduction.

Abstract: A method for removing germanium suboxide between a germanium (Ge) substrate and a dielectric layer made of metal oxide includes causing a supercritical fluid composition that includes a supercritical carbon dioxide fluid and an oxidant to diffuse into the germanium suboxide such that metal residues in the dielectric layer, the germanium suboxide and the oxidant are subjected to a redox reaction so as to reduce the germanium suboxide into germanium.

Abstract: The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack.

Abstract: The present invention relates to a high gain complementary inverter with ambipolar thin film transistors and fabrication thereof, comprising: a gate layer, a silica layer, a first active layer, a first source, a first drain, a second active layer, a second source and a second drain for fabrication cost and complexity reduction.

Abstract: A semiconductor structure and a fabricating method thereof are provided. The fabricating method includes forming a gate, a source, and a drain on a substrate and forming an oxide semiconductor material between the gate and the source and drain. The oxide semiconductor material is formed by performing a deposition process, and nitrogen gas is introduced before the deposition process is completely performed, so as to form oxide semiconductor nitride on the oxide semiconductor material.

Abstract: The invention discloses a method for forming an interfacial passivation layer on the Ge semiconductor. The supercritical CO2 fluids is used to form an interfacial passivation layer between Ge channel and gate insulator layer, and improve the dielectric characteristics of gate insulator after high-temperature thermal annealing process.

Abstract: A method of fabricating a thin film transistor (TFT) includes first providing a strip-shaped silicon island which is a thin film region with a predetermined long side and short side. Next, the strip-shaped silicon island is subject to an ion implantation to form a first ion doping region and a second ion doping region. The first and second ion doping regions, respectively used as the source and the drain of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate. A gate is formed over the strip-shaped silicon island and the first and second ion doping regions, wherein the gate is substantially parallel to the direction of the short side.

Abstract: A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined long side and short side, and farther has a plurality of lateral grain boundaries substantially parallel to the short side of the silicon island. The gate is located over the silicon island and substantially parallel to the lateral grain boundaries. The first and second ion doping regions, used as source/drain regions of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate.

Abstract: A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.

Abstract: A method of fabricating a thin film transistor (TFT) includes first providing a strip-shaped silicon island which is a thin film region with a predetermined long side and short side. Next, the strip-shaped silicon island is subject to an ion implantation to form a first ion doping region and a second ion doping region. The first and second ion doping regions, respectively used as the source and the drain of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate. A gate is formed over the strip-shaped silicon island and the first and second ion doping regions, wherein the gate is substantially parallel to the direction of the short side.

Abstract: A method for manufacturing copper wires on a substrate for a flat panel display device is disclosed. The method comprises following steps: providing a substrate; forming a seed layer on the surface; forming a patterned photoresist on the surface of the seed layer to expose a part of the seed layer; and plating a copper layer on the exposed part of the seed layer. As the copper layer is plated, an electrolyte solution comprises a sulfur-containing compound is used. The angle between the surface of the copper layer and the contact surface of the seed layer is greater than 0 degree and less than 90 degree. Through the method illustrated above, the film step-coverage in the following process can be improved, the generated voids in device can be reduced, the manufacturing steps can be simplified, and the complicated etching process can be avoided.

Abstract: A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined long side and short side, and farther has a plurality of lateral grain boundaries substantially parallel to the short side of the silicon island. The gate is located over the silicon island and substantially parallel to the lateral grain boundaries. The first and second ion doping regions, used as source/drain regions of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate.

Abstract: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.

Abstract: A method for manufacturing copper wires on a substrate for a flat panel display device is disclosed. The method comprises following steps: providing a substrate; forming a seed layer on the surface; forming a patterned photoresist on the surface of the seed layer to expose a part of the seed layer; and plating a copper layer on the exposed part of the seed layer. As the copper layer is plated, an electrolyte solution comprises a sulfur-containing compound is used. The angle between the surface of the copper layer and the contact surface of the seed layer is greater than 0 degree and less than 90 degree. Through the method illustrated above, the film step-coverage in the following process can be improved, the generated voids in device can be reduced, the manufacturing steps can be simplified, and the complicated etching process can be avoided.