Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.

Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: A dynamic prediction model establishment method, an electric device and a user interface are provided. The dynamic prediction model establishment method includes the following steps. An integration model is established by a processing device according to at least one auxiliary data set. The integration model is modified as a dynamic prediction model by the processing device according to a target data set. A sampling point recommendation information is provided by the processing device according to an error degree or an uncertainty degree between the at least one auxiliary data set and the target data set.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: An optimum sampling search system and method with risk assessment, and a graphical user interface are provided. The optimum sampling search system includes a data acquisition unit, an objective satisfaction score calculation unit, a constraint satisfaction probability calculation unit, a sampling risk evaluation unit, and an adjusting unit. If the constraint satisfaction probability of a recommended sampling parameter is between a first predetermined value and a second predetermined value, the recommended sampling parameter is adjusted, by the adjusting unit, to optimize a constraint satisfaction probability model.

Abstract: A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the semiconductor structure includes forming a fin structure extending from a front side of a substrate, recessing a source region of the fin structure to form a source opening, forming a semiconductor plug under the source opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize the substrate, replacing the amorphized substrate with a dielectric layer, and replacing the semiconductor plug with a backside source contact. By performing the PAI process, crystalline semiconductor is amorphized and may be substantially removed. Thus, the performance and reliability of the semiconductor structure may be advantageously improved.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.

Abstract: A warehouse picking system and a warehouse picking method are provided. The warehouse picking system includes multiple cargo management stations and a management device. The management device receives multiple orders including at least one cargo, calculates an order score of each order by using an order score function; selects at least one order as a target order according to the order scores so as to determine a target cargo management station adapted for processing the target order; selects a cargo picking box storing at least one cargo in the target order from the cargo picking boxes of the target cargo management station to serve as candidate cargo picking boxes; and determines a target cargo picking box adapted for picking the cargo in the target order according to a workload of cargo picking equipment, a workload of cargo transportation equipment, and a disposition of each candidate cargo picking box.

Abstract: A parameter optimization device includes a data acquisition module, a sampling function calculation module, a clustering module and a parameter recommendation module. The data acquisition module is configured to acquire several input parameter values and corresponding several measurement output values. The sampling function calculation module is configured to obtain several sampling function values according to the input parameter values and the measurement output values. The clustering module is configured to obtain several parameter groups according to the input parameter values and the sampling function values. The parameter recommendation module is configured to obtain several recommended parameter values from at least one of the parameter groups.

Abstract: A multi-camera positioning and dispatching system includes a plurality of cameras and processing device. The cameras are disturbed over an indoor space having a plurality of areas; the cameras are corresponding to the areas and capture the images of the areas respectively. The processing device converts the pixel coordinates of the image of the camera corresponding to each area into the camera coordinates of the area, and converts the cameras coordinates of the area into the world coordinates of the area so as to integrate the images with one another and obtain a panoramic map, defined by a world coordinate system, of the indoor space. The processing device projects the working unit in the image captured by any one of the cameras to the panoramic map. The system can achieve positioning function via the panoramic map so as to optimize indoor environment management and save manpower.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.

Abstract: A packet information analysis method suitable for a device measuring and monitoring network traffic in real-time. The method includes: obtaining network data including a combination of multiple network packet header information; generating an index parameter according to packet header information of a monitored network packet in the network packets; querying at least one reference table according to the index parameter to obtain a first reference value and an offset correction value corresponding to the index parameter in the at least one reference table; obtaining a second reference value according to the first reference value and the offset value; and obtaining an evaluation value according to the second reference value. The evaluation value reflects the distribution status of a measuring and monitoring item in the network packets.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

Abstract: An ensemble learning prediction method includes: establishing a plurality of base predictors based on a plurality of training data; initializing a plurality of sample weights of a plurality of sample data and initializing a processing set; in each iteration round, based on the sample data and the sample weights, establishing a plurality of predictor weighting functions of the predictors in the processing set and predicting each of the sample data by each of the predictors in the processing set for identifying a prediction result; evaluating the predictor weighting functions, and selecting a respective target predictor weighting function from the predictor weighting functions established in each iteration round and selecting a target predictor from the predictors in the processing set to update the processing set and to update the sample weights of the sample data.