Patents by Inventor Po-Yu Huang

Po-Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220340177
    Abstract: Various embodiments for systems and methods for cooperative driving of connected autonomous vehicles using responsibility-sensitive safety (RSS) rules are disclosed herein. The CAV system integrates proposed RSS rules with CAV's motion planning algorithm to enable cooperative driving of CAVs. The CAV system further integrates a deadlock detection and resolution system for resolving traffic deadlocks between CAVs. The CAV system reduces redundant calculation of dependency graphs.
    Type: Application
    Filed: March 16, 2022
    Publication date: October 27, 2022
    Applicant: National Taiwan University
    Inventors: Mohammad Khayatian, Mohammadreza Mehrabian, Harshith Allamsetti, Kai- Wei Liu, Po-Yu Huang, Chung-Wei Lin, Aviral Shrivastava
  • Publication number: 20220310455
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Po-Yu Huang, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220272016
    Abstract: A packet information analysis method suitable for a device measuring and monitoring network traffic in real-time. The method includes: obtaining network data including a combination of multiple network packet header information; generating an index parameter according to packet header information of a monitored network packet in the network packets; querying at least one reference table according to the index parameter to obtain a first reference value and an offset correction value corresponding to the index parameter in the at least one reference table; obtaining a second reference value according to the first reference value and the offset value; and obtaining an evaluation value according to the second reference value. The evaluation value reflects the distribution status of a measuring and monitoring item in the network packets.
    Type: Application
    Filed: June 16, 2021
    Publication date: August 25, 2022
    Applicant: Chung Yuan Christian University
    Inventors: Yu-Kuen Lai, Po-Yu Huang
  • Publication number: 20220238660
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the semiconductor structure includes forming a fin structure extending from a front side of a substrate, recessing a source region of the fin structure to form a source opening, forming a semiconductor plug under the source opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize the substrate, replacing the amorphized substrate with a dielectric layer, and replacing the semiconductor plug with a backside source contact. By performing the PAI process, crystalline semiconductor is amorphized and may be substantially removed. Thus, the performance and reliability of the semiconductor structure may be advantageously improved.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Po-Yu Huang, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220238713
    Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.
    Type: Application
    Filed: July 23, 2021
    Publication date: July 28, 2022
    Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220199530
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 23, 2022
    Inventors: Po-Yu Huang, Chia-Hsien Yao, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220171349
    Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 2, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Yu HUANG, Chun-Fang CHEN, Hong-Chi KU, Te-Ming CHEN, Chien-Liang LAI, Sen-Chia CHANG
  • Publication number: 20220163837
    Abstract: An electronic device is provided. The electronic device includes a frame and a protective substrate, and the protective substrate is adhered to the frame. The protective substrate has a side surface, and a surface roughness of the side surface is greater than or equal to 1 micrometer and less than or equal to 15 micrometers.
    Type: Application
    Filed: October 14, 2021
    Publication date: May 26, 2022
    Inventors: Li-Chi LO, Po-Yu HUANG
  • Publication number: 20220150406
    Abstract: A multi-camera positioning and dispatching system is provided, which includes a plurality of cameras and processing device. The cameras are disturbed over an indoor space having a plurality of areas; the cameras are corresponding to the areas and capture the images of the areas respectively. The processing device converts the pixel coordinates of the image of the camera corresponding to each area into the camera coordinates of the area, and converts the cameras coordinates of the area into the world coordinates of the area so as to integrate the images with one another and obtain a panoramic map, defined by a world coordinate system, of the indoor space. The processing device projects the working unit in the image captured by any one of the cameras to the panoramic map. The system can achieve positioning function via the panoramic map so as to optimize indoor environment management and save manpower.
    Type: Application
    Filed: March 10, 2021
    Publication date: May 12, 2022
    Inventors: LI-YI LIU, PO-YU HUANG, WEI-KANG LIANG, SONG-LIN LI
  • Publication number: 20220139828
    Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
  • Patent number: 11319410
    Abstract: The present invention provides an amic acid ester oligomer having a structure of Formula (1) or (1?): wherein G, P, R, Rx, D, E and m are those as defined in the specification. The present invention also provides a polyimide precursor composition or a photosensitive polyimide precursor composition comprising the amic acid ester oligomer, as well as a polyimide prepared from the composition.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 3, 2022
    Assignee: ETERNAL MATERIALS CO., LTD.
    Inventors: Po-Yu Huang, Chung-Jen Wu, Meng-Yen Chou, Chang-Hong Ho, Shun-Jen Chiang, Chung-Kai Cheng
  • Patent number: 11276643
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yu Huang, Jason Yao, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220028786
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Inventors: Po-Yu Huang, Jason Yao, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11227830
    Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
  • Patent number: 11198792
    Abstract: The present invention relates to a method for preparing a patterned polyimide coverlay on a substrate. The method includes: providing a polyimide dry film including a carrier and a non-photosensitive polyimide layer on the carrier, the non-photosensitive polyimide layer containing (i) a polyimide precursor or soluble polyimide and (ii) a solvent; forming a predetermined pattern in the polyimide dry film; laminating the patterned polyimide dry film onto a substrate in such a manner that the non-photosensitive polyimide layer faces the substrate; and forming a patterned polyimide coverlay by heating.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: December 14, 2021
    Assignee: ETERNAL MATERIALS CO., LTD.
    Inventors: Chung-Kai Cheng, Chung-Jen Wu, Meng-Yen Chou, Chang-Hong Ho, Po-Yu Huang, Shun-Jen Chiang
  • Publication number: 20210367043
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Patent number: 11177212
    Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Publication number: 20210320061
    Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 14, 2021
    Inventors: Po-Yu HUANG, Shih-Che LIN, Chao-Hsun WANG, Kuo-Yi CHAO, Mei-Yun WANG
  • Patent number: 11107896
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Patent number: 11106190
    Abstract: A system and method for predicting remaining lifetime of a component of equipment is provided. The prediction system includes a data module, a feature module, a current data-based prediction module, a historical data-based prediction module, and a confidence module. The data module obtains a test sensor data of the component of equipment. The feature module obtains a historical health indicator and the current-health indicator. The current data-based prediction module obtains a first predicted remaining lifetime and a first prediction confidence according to the current-health indicator. The historical data-based prediction module obtains a second predicted remaining lifetime and a second prediction confidence according to the historical health indicator.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 31, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Yu Huang, Chuang-Hua Chueh, Jia-Min Ren