Patents by Inventor Po-Yu Lin

Po-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250123963
    Abstract: A data storage device that performs instruction scheduling at the device side. The data storage device has a non-volatile memory, and a controller configured to operate the non-volatile memory in response to requests from the host side. The controller has an instruction cache operative to cache instructions issued from the host side. Based on information carried by the instructions, the controller schedules and executes the instructions to operate the non-volatile memory.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 17, 2025
    Inventors: Po-Yu LIN, Jhih-Shun YANG
  • Patent number: 12268023
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Tzu-Hua Chiu, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Patent number: 12191369
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
  • Patent number: 12170202
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: January 2, 2023
    Date of Patent: December 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20240363350
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Publication number: 20240363714
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hao CHENG, Wei-Yang LEE, Tzu-Hua CHIU, Wei-Han FAN, Po-Yu LIN, Chia-Pin LIN
  • Patent number: 12051732
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hao Cheng, Wei-Yang Lee, Tzu-Hua Chiu, Wei-Han Fan, Po-Yu Lin, Chia-Pin Lin
  • Publication number: 20240186373
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Application
    Filed: February 7, 2024
    Publication date: June 6, 2024
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20230378304
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
  • Publication number: 20230141521
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: January 2, 2023
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20230063612
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Po-Yu Lin, Tzu-Hua Chiu, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Publication number: 20230052084
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hao CHENG, Wei-Yang LEE, Tzu-Hua CHIU, Wei-Han FAN, Po-Yu LIN, Chia-Pin LIN
  • Publication number: 20230018480
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack over a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure over the first nanostructure and passing through the gate stack. The first nanostructure is thicker than the second nanostructure. The semiconductor device structure includes a stressor structure over the fin and connected to the first nanostructure and the second nanostructure.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hao CHENG, Wei-Yang LEE, Tzu-Hua CHIU, Wei-Han FAN, Po-Yu LIN, Chia-Pin LIN
  • Publication number: 20230019386
    Abstract: Semiconductor devices and methods are provided. In an embodiment, a semiconductor device includes first nanostructures directly over a first portion of a substrate and second nanostructures directly over a second portion of the substrate, n-type source/drain features coupled to the first nanostructures and p-type source/drain features coupled to the second nanostructures, and an isolation structure disposed between the first portion of the substrate and the second portion of the substrate. The isolation structure includes a first smiling region in direct contact with the first portion of the substrate and having a first height. The isolation structure also includes a second smiling region in direct contact with the second portion of the substrate and having a second height, the first height is greater than the second height.
    Type: Application
    Filed: May 24, 2022
    Publication date: January 19, 2023
    Inventors: Kuan-Hao Cheng, Chia-Pin Lin, Wei-Yang Lee, Tzu-Hua Chiu, Wei-Han Fan, Po-Yu Lin
  • Patent number: 11545363
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20220317771
    Abstract: The embodiments of the disclosure provide a method for tracking trackers and a host. The method includes: obtaining a first relative pose between a first tracker and a second tracker; in response to determining that the first relative pose is stable, determining whether a first pose of the first tracker is trackable; and in response to determining that the first pose of the first tracker is untrackable, determining the first pose of the first tracker based on a second pose of the second tracker and the first relative pose.
    Type: Application
    Filed: March 15, 2022
    Publication date: October 6, 2022
    Applicant: HTC Corporation
    Inventors: Chih Chien Chen, Chun-Kai Huang, Po-Yu Lin
  • Publication number: 20220320276
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Application
    Filed: August 5, 2021
    Publication date: October 6, 2022
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20220320307
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.
    Type: Application
    Filed: September 1, 2021
    Publication date: October 6, 2022
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
  • Patent number: 11232311
    Abstract: A method providing guidance to a vehicle for parking includes: obtaining information of potential parking space. Information of the parking space includes likelihood of finding unoccupied parking space and navigating to the parking space according to the information of parking space. The information of the parking space guides a driver to quickly find the parking space, thereby reducing parking time, improving parking space utilization, and efficiency of road traffic management. Calculating the likelihood of finding an unoccupied space is of great assistance to a driver.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 25, 2022
    Assignee: Shenzhen Fugui Precision Ind. Co., Ltd.
    Inventor: Po-Yu Lin