Patents by Inventor Po-Yu Lin

Po-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240371955
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Kai-Hsuan LEE, Shih-Che LIN, Po-Yu HUANG, Shih-Chieh WU, I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20240363421
    Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Yu LIN, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
  • Publication number: 20240363714
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hao CHENG, Wei-Yang LEE, Tzu-Hua CHIU, Wei-Han FAN, Po-Yu LIN, Chia-Pin LIN
  • Publication number: 20240363350
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Publication number: 20240353635
    Abstract: A pluggable optical packaging structure is provided, including: a substrate, a carrier ring, at least one optical connection assembly and a cover plate; the substrate includes at least one electronic integrated circuit (EIC) and at least one photonic integrated circuit (PIC); the carrier ring is located on the substrate, and the EIC and PIC are enclosed by the carrier ring; the optical connection assembly includes at least one socket, at least one connector, a plurality of optical fibers and at least one optical fiber array connector, the socket is located in a partial section of the carrier ring, the connector is in the socket, the optical fibers has one end coupled to the connector, the other end coupled to the fiber array connector, and is coupled to the PIC through the fiber array connector; the cover plate is located on the carrier ring and extends inwardly to above the PIC.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 24, 2024
    Inventors: Ting-Ta Hu, Po-Yi Wu, Chieh-Yu Fang, Ting-Yan Lin, Chia-Kuo Chen
  • Publication number: 20240353632
    Abstract: The present invention provides an optical interposer for chip connection including a first total internal reflective layer, a waveguide and a second total internal reflective layer. The optical interposer is disposed above a first photonic integrated circuit chip and a second photonic integrated circuit chip, coupling the first photonic integrated circuit chip and the second photonic integrated circuit chip. The refractive indices of the first total internal reflective layer and the second total internal reflective layer are lower than the waveguide, making a light signal perform repetitive total internal reflections at the junctions between materials and advance in a zigzag shape within the waveguide, and further transmits between the first photonic integrated circuit chip and the second photonic integrated circuit chip.
    Type: Application
    Filed: May 26, 2023
    Publication date: October 24, 2024
    Inventors: Ting-Ta Hu, Po-Yi Wu, Chieh-Yu Fang, Ting-Yan Lin
  • Publication number: 20240355730
    Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
  • Publication number: 20240345329
    Abstract: A light-coupling device includes an interposer, an optical chip, an optical waveguide element and a fiber array connector. The optical chip includes a waveguide layer with a light-emitting surface located aside the optical chip. The optical waveguide element includes an incident surface facing the light-emitting surface, an emergent surface located atop, and a reflective surface located inside. A light beam emitted horizontally from the light-emitting surface enters the optical waveguide element through the incident surface, totally reflected through the reflective surface and is output as a parallel light beam in the vertical direction through the emergent surface. The fiber array connector includes an optical waveguide lens and a plurality of fibers. The optical waveguide lens faces the emergent surface. One of both horizontal sides of the optical waveguide lens is a tilted reflective surface while the other is a light-coupling surface aligned with the fibers.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 17, 2024
    Inventors: Ting-Ta Hu, Po-Yi Wu, Chieh-Yu Fang, Ting-Yan Lin
  • Publication number: 20240349471
    Abstract: The present application provides a learning method for plug-in depth including steps of: (a) utilizing a robot arm to take an electronic component with a plurality of pins; (b) utilizing a first visual device to identify a pin distance; (c) utilizing a second visual device to identify a hole distance; (d) inserting the plurality of pins into the corresponding plurality of holes with a predetermined depth according to the pin distance and the hole distance; (e) determining whether the plurality of pins are inserted into the plurality of holes, performing step (f) when the determination result is satisfied, and performing step (g) when the determination result is not satisfied; (f) recording the predetermined depth and performing the step (a) again; (g) calibrating the predetermined depth and performing the step (a) again; and (h) completing the learning of the plug-in depth after the step (f) is performed multiple times successively.
    Type: Application
    Filed: July 13, 2023
    Publication date: October 17, 2024
    Inventors: Jian-Jang Lai, Po-Yu Chen, Chien-Ta Lin
  • Patent number: 12118653
    Abstract: A system, method, and computer program product are provided for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: October 15, 2024
    Assignee: MediaTek Inc.
    Inventors: Po-Yu Huang, Shih-Chin Lin, Jen-Jung Cheng, Tu-Hsiu Lee
  • Publication number: 20240337793
    Abstract: The present invention provides a semiconductor structure including a substrate, a metal reflective layer, a UV glue layer, and an element. The metal reflective layer is placed on the surface of the substrate, and the UV glue layer is placed on the surface of the metal reflective layer. The element is manufactured by light-transparent material. The UV glue layer adheres the element to the metal reflective layer. By so, in the light-curing process, the curing of the UV glue is accelerated due to the metal reflective layer reflecting an ultraviolet ray.
    Type: Application
    Filed: May 12, 2023
    Publication date: October 10, 2024
    Inventors: Ting-Ta Hu, Po-Yi Wu, Chieh-Yu Fang, Ting-Yan Lin
  • Publication number: 20240332421
    Abstract: A semiconductor device includes a first fin structure, an insulating structure, a first groove and a gate structure. The first fin structure is extended along a first direction on a substrate. The insulating structure surrounds the first fin structure. The first groove is extended along the first direction and disposed between the first fin structure and the insulating structure. The first groove exposes a first portion of the substrate. The gate structure is extended along a second direction on the first fin structure. At least a portion of the gate structure is disposed in the first groove. The gate structure includes a gate dielectric layer disposed on the first fin structure and the first portion of the substrate.
    Type: Application
    Filed: July 31, 2023
    Publication date: October 3, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Yu Yang, Chun-Hsien Lin
  • Publication number: 20240317511
    Abstract: An automatic pick-and-place system is provided, including a feeding device, a visual pattern formed on a fixed part of the feeding device, a manipulator, and a processing unit. An electronic component can be held between the fixed part and a gripping part of the feeding device. A visual module on the manipulator captures an image of the visual pattern, and the processing unit calculates the coordinate value of the electronic component. Thus, the manipulator can move to the target position and pick up the electronic element according to the coordinate value.
    Type: Application
    Filed: September 1, 2023
    Publication date: September 26, 2024
    Inventors: Chien-Ta LIN, Jie-Shiou TSAI, Po-Yu CHEN, Jian-Jang LAI
  • Publication number: 20240302579
    Abstract: An electronic device is provided. The electronic device includes a substrate, a first light-shielding layer, a second light-shielding layer, a third light-shielding layer and an optical sensing element. The first light-shielding layer is disposed on the substrate and has a first opening. The second light-shielding layer is disposed on the first light-shielding layer and has a second opening. The third light-shielding layer is disposed on the second light-shielding layer and has a third opening. The optical sensing element is disposed on the substrate, and overlapped with the first opening. In addition, in a top-view diagram, centers of the first opening, the second opening and the third opening are separated from each other along a first direction, and the first direction is a line connecting a center of the first opening and a center of the third opening.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Inventors: Te-Yu LEE, Yu-Tsung LIU, Wei-Ju LIAO, Po-Hsin LIN, Chao-Yin LIN
  • Patent number: 12087690
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 12083679
    Abstract: A stabilization method incorporated with a mobile robot having a body, a plane-pressure sensor, and a movement mechanism is disclosed and includes the following steps: sensing and obtaining a pressure distribution of the body through the plane-pressure sensor; computing a center of gravity (CoG) position of the body in accordance with the pressure distribution; determining whether the CoG position is located within a steady zone pre-defined upon the body; and, providing a reverse force toward a CoG offset direction of the CoG position when the CoG position is determined to be off the steady zone.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: September 10, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Cheng-Hao Huang, Po-Chiao Huang, Han-Ching Lin, Shi-Yu Wang
  • Publication number: 20240296272
    Abstract: A method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Inventors: Pin-Dai SUE, Po-Hsiang HUANG, Fong-Yuan CHANG, Chi-Yu LU, Sheng-Hsiung CHEN, Chin-Chou LIU, Lee-Chung LU, Yen-Hung LIN, Li-Chun TIEN, Yi-Kan CHENG
  • Patent number: 12080769
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Hsuan Lee, Shih-Che Lin, Po-Yu Huang, Shih-Chieh Wu, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240284703
    Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 22, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Chung-Chih Wu, Po-Jui Chen, Hoang Yan Lin, Guo-Dong Su, Wei-Kai Lee, Chi-Jui Chang, Wan-Yu Lin, Byung Sung Kwak, Robert Jan Visser
  • Patent number: 12062576
    Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: August 13, 2024
    Inventors: Han-Yu Lin, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih