Patents by Inventor Po-Yuan Chen

Po-Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220369475
    Abstract: A circuit board includes a circuit substrate, a solder, and a surrounding portion. The circuit substrate includes a connecting pad. The solder is formed on a surface of the connecting pad. The surrounding portion is formed on the surface of the connecting pad and cooperates with the connecting pad to form a groove receiving the solder. The surrounding portion surrounds the solder and is spaced from the solder. A method for manufacturing a circuit board is also provided.
    Type: Application
    Filed: May 26, 2021
    Publication date: November 17, 2022
    Inventors: YONG-CHAO WEI, PO-YUAN CHEN
  • Publication number: 20220369467
    Abstract: A circuit board includes a circuit substrate, at least one metal pad, and a tin bar corresponding to each of the at least one metal pad. Each of the at least one metal pad is formed on a side of the circuit substrate and is electrically connected to the circuit substrate. A surface of the metal pad facing away from the circuit substrate is recessed toward the circuit substrate to from a recess. The tin bar is received in the recess. A method for manufacturing a circuit board is also provided.
    Type: Application
    Filed: May 26, 2021
    Publication date: November 17, 2022
    Inventors: PO-YUAN CHEN, YONG-CHAO WEI
  • Patent number: 11337614
    Abstract: A multi-target vital sign detection system includes a transmitter, a receiver and a processor. The transmitter is configured to transmit a millimeter wave signal to a detection area, and the receiver is configured to receive a reflecting millimeter wave signal reflected by a plurality of targets in the detection area. The processor is configured to: generate signal strength versus distance data by analyzing the received reflecting millimeter wave signal; perform an extreme value reserving process to generate signal extreme value versus distance data; perform a peak search algorithm to obtain a peak list including a plurality of peak values and a plurality of corresponding peak distances; generate a distance array including a plurality of distance variables; and perform a vital sign detection algorithm to generate multiple sets of vital sign data.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 24, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Tse-Hsuan Wang, Po-Yuan Chen, Chao-Hsu Wu
  • Publication number: 20200268257
    Abstract: A multi-target vital sign detection system includes a transmitter, a receiver and a processor. The transmitter is configured to transmit a millimeter wave signal to a detection area, and the receiver is configured to receive a reflecting millimeter wave signal reflected by a plurality of targets in the detection area. The processor is configured to: generate signal strength versus distance data by analyzing the received reflecting millimeter wave signal; perform an extreme value reserving process to generate signal extreme value versus distance data; perform a peak search algorithm to obtain a peak list including a plurality of peak values and a plurality of corresponding peak distances; generate a distance array including a plurality of distance variables; and perform a vital sign detection algorithm to generate multiple sets of vital sign data.
    Type: Application
    Filed: December 20, 2019
    Publication date: August 27, 2020
    Inventors: CHIEN-YI WU, TSE-HSUAN WANG, PO-YUAN CHEN, CHAO-HSU WU
  • Patent number: 9690012
    Abstract: An anti-reflection structure includes a substrate including a planar portion, a protrusion portion disposed over the planar portion, and a coating layer, wherein the protrusion portion is integrated with the planar portion, and the coating layer conformably covers the planar portion and the protrusion portion.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: June 27, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Tai-Nien Ko, I-Chun Cheng, Po-Yuan Chen, Yun-Shiuan Li, Chia-Yun Chou
  • Patent number: 9577146
    Abstract: A light-emitting element comprises: a first semiconductor stack having a first conductivity type; an active layer formed on the first semiconductor stack; a second semiconductor stack having a second conductivity type formed on the active layer; and a first current-spreading layer having the first conductivity type interposed in the second semiconductor stack.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: February 21, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Po Yuan Chen, Wen Ming Tsao, Chih Chun Ke
  • Publication number: 20160315221
    Abstract: A light-emitting element comprises: a first semiconductor stack having a first conductivity type; an active layer formed on the first semiconductor stack; a second semiconductor stack having a second conductivity type formed on the active layer; and a first current-spreading layer having the first conductivity type interposed in the second semiconductor stack.
    Type: Application
    Filed: April 24, 2015
    Publication date: October 27, 2016
    Inventors: Po Yuan CHEN, Wen Ming TSAO, Chih Chun KE
  • Publication number: 20160041309
    Abstract: An anti-reflection structure includes a substrate including a planar portion, a protrusion portion disposed over the planar portion, and a coating layer, wherein the protrusion portion is integrated with the planar portion, and the coating layer conformably covers the planar portion and the protrusion portion.
    Type: Application
    Filed: August 4, 2015
    Publication date: February 11, 2016
    Inventors: Tai-Nien KO, I-Chun CHENG, Po-Yuan CHEN, Yun-Shiuan LI, Chia-Yun CHOU
  • Publication number: 20150313381
    Abstract: A luminous photo frame includes an outer frame assembly having a light transmittable section, a reflector plate arranged in the outer frame assembly, a light guide plate arranged between the reflector plate and the light transmittable section, a light emission element opposing an edge of the light guide plate, a brightness enhancement film arranged between the light guide plate and the light transmittable section, and a light-transmitting surface panel mounted to the outer frame assembly to be adjacent to the light transmittable section. To use, a traditional photo is first deposited at one side of the light-transmitting surface panel and the light emission element is activated to emit light, which is guided and spread by the light guide plate and reflected by the reflector plate for projecting toward the light transmittable section to pass through the brightness enhancement film and transmit through the light transmittable section and the traditional photo.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 5, 2015
    Inventor: Po-Yuan Chen
  • Patent number: 8937486
    Abstract: A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 20, 2015
    Assignee: National Tsing Hua University
    Inventors: Cheng-Wen Wu, Po-Yuan Chen, Ding-Ming Kwai, Yung-Fa Chou
  • Publication number: 20130293255
    Abstract: A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range.
    Type: Application
    Filed: July 11, 2013
    Publication date: November 7, 2013
    Inventors: Cheng-Wen Wu, Po-Yuan Chen, Ding-Ming Kwai, Yung- Fa Chou
  • Patent number: 8531199
    Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: September 10, 2013
    Assignee: National Tsing Hua University
    Inventors: Cheng Wen Wu, Po Yuan Chen, Ding Ming Kwai, Yung Fa Chou
  • Patent number: 8411473
    Abstract: A three-phase power supply with a three-phase three-level DC/DC converter includes a full-bridge thyristor converter with three-set four in-series power switch elements, a three-phase isolated transformer, a full-bridge rectifier, a rectifying circuit, and a low-pass filtering circuit. The three-phase power supply is used to deliver power energy from the AC input voltage to the load. The power switch elements, which separated to each other at 120-degree phase differences, are controlled through a phase shift scheme. Therefore, the three-level circuit structure is provided to reduce withstanding voltage of the power switch elements, further the zero-voltage switching (ZVS) is achieved by the isolated transformer and the power switch elements to increase the efficiency of the DC/DC converter.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 2, 2013
    Assignee: Allis Electric Co., Ltd.
    Inventors: Chaur-Ping Cheng, Chih-Hsing Fang, Wen-Wei Chan, Po-Yuan Chen
  • Patent number: 8383843
    Abstract: Disclosed herein is a method for preparing a coumarin compound of formula (F), in which R1, R2, and R3 are independently H, C1˜C7 alkoxy, C1˜C7 alkyl, phenoxy, benzyloxy, or a halogen atom; R4 is an alkyl group; and Ar is an optionally substituted aryl group, the method including: treating a chromene compound having the following formula (E) with an acid in the presence of water. A chromene compound of formula (E) and a method for preparing the chromene compound of formula (E) are also disclosed.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: February 26, 2013
    Assignee: Kaohsiung Medical University
    Inventors: Eng-Chi Wang, Jui-Chi Tsai, Sie-Rong Li, Po-Yuan Chen
  • Patent number: 8281095
    Abstract: A data storage system and the backup method thereof are provided. The data storage system includes a storage device and a storage controller. The storage controller is coupled to the storage device and used for dividing the storage device into a primary data block and a backup data block and setting the data storage system to operate under one of a real time backup mode and a non-real time backup mode. Under the non-real time backup mode, the storage controller backups the data stored in the primary data block to the backup data block when the data storage system is idle.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 2, 2012
    Assignee: Prolific Technology Inc.
    Inventors: Po-Yuan Chen, Jue-Wen Liu
  • Publication number: 20120155124
    Abstract: A three-phase power supply with a three-phase three-level DC/DC converter includes a full-bridge thyristor converter with three-set four in-series power switch elements, a three-phase isolated transformer, a full-bridge rectifier, a rectifying circuit, and a low-pass filtering circuit. The three-phase power supply is used to deliver power energy from the AC input voltage to the load. The power switch elements, which separated to each other at 120-degree phase differences, are controlled through a phase shift scheme. Therefore, the three-level circuit structure is provided to reduce withstanding voltage of the power switch elements, further the zero-voltage switching (ZVS) is achieved by the isolated transformer and the power switch elements to increase the efficiency of the DC/DC converter.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventors: Chaur-Ping CHENG, Chih-Hsing Fang, Wen-Wei Chan, Po-Yuan Chen
  • Publication number: 20120088923
    Abstract: Disclosed herein is a method for preparing a coumarin compound of formula (F), in which R1, R2, and R3 are independently H, C1˜C7 alkoxy, C1˜C7 alkyl, phenoxy, benzyloxy, or a halogen atom; R4 is an alkyl group; and Ar is an optionally substituted aryl group, the method including: treating a chromene compound having the following formula (E) with an acid in the presence of water. A chromene compound of formula (E) and a method for preparing the chromene compound of formula (E) are also disclosed.
    Type: Application
    Filed: October 11, 2010
    Publication date: April 12, 2012
    Applicant: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Eng-Chi Wang, Jui-Chi Tsai, Sie-Rong Li, Po-Yuan Chen
  • Patent number: 8076210
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: December 13, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
  • Patent number: 8053847
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: November 8, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
  • Publication number: 20110159658
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien