Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Abstract: A data storage system and the backup method thereof are provided. The data storage system includes a storage device and a storage controller. The storage controller is coupled to the storage device and used for dividing the storage device into a primary data block and a backup data block and setting the data storage system to operate under one of a real time backup mode and a non-real time backup mode. Under the non-real time backup mode, the storage controller backups the data stored in the primary data block to the backup data block when the data storage system is idle.

Abstract: An apparatus provided with programmable scan chains includes a scan chain having a scan input port and a scan output port, a plurality of first I/O ports, an input port selector for selecting one of the plurality of first I/O ports to be coupled to the scan input port, a plurality of second I/O ports, an output port selector for selecting one of the plurality of second I/O ports to be coupled to said scan output port. Further, an apparatus provided with programmable scan chains includes N scan chains, each scan chain having a scan input port and scan output port, M first I/O ports, an input port selector for selecting N of the first I/O ports to be coupled to the N scan input ports, K second I/O ports, and an output port selector for selecting N of the second I/O ports to be coupled to the N scan output ports.

Abstract: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.

Abstract: An apparatus provided with programmable scan chains includes a scan chain having a scan input port and a scan output port, a plurality of first I/O ports, an input port selector for selecting one of the plurality of first I/O ports to be coupled to the scan input port, a plurality of second I/O ports, an output port selector for selecting one of the plurality of second I/O ports to be coupled to said scan output port. Further, an apparatus provided with programmable scan chains includes N scan chains, each scan chain having a scan input port and scan output port, M first I/O ports, an input port selector for selecting N of the first I/O ports to be coupled to the N scan input ports, K second I/O ports, and an output port selector for selecting N of the second I/O ports to be coupled to the N scan output ports.

Abstract: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.

Abstract: A stepper motor has a housing having a chamber therein. The housing frame has an annular plate and a bottom plate coupled with the annular plate and an included angle between the annular plate and the bottom plate is set at about ninety degree. A stator has a space at a center thereof and wound coils thereon to generate induced magnetic field in the space. The stator has a circumference closely attached on the inner side of the annular plate of the housing. A rotor is received in the inner space of the stator to be driven for rotation by the induced magnetic field. A motor front-plate is coupled with the housing to close the chamber, and a shaft has an end thereof coupled with the rotor for rotating along with the rotor.

Abstract: An IC card of flash memory according to the present invention comprises an array of flash memory. The array has a plurality of pages having flash memory cells erased simultaneously. The pages comprise a relative-large page and a relative-small page. The number of the flash memory cells in the relative-large page is larger than that in the relative-small page. Seldom-change data codes, longer data codes and programs are stored into the relative-large pages. On the other hand, shorter data codes and frequently-changed data codes are stored into the relative-small pages. A better reliability can be achieved according to the present invention.

Abstract: A control circuit and method for managing multicast packets is implemented in a network switch to improve the efficiency of bandwidth utilization. The control circuit comprises an internal control buffer which is subdivided into multiple storage sections. Each storage section consists of buffer-control records including valid bit, counter value, control pointer, and tag number. When the tag number of a coming multicast packet indicates that the internal control buffer is full, the control data of the coming multicast packet will be copied to an external control memory. On the other hand, the control data of the coming multicast packet will be directly stored in the control buffer if otherwise. After each multicast packet transmission, the control data in the control buffer can be accessed and updated. Consequently, the traffic between the network switch and the external memories can be reduced to the minimum, thereby to improve the efficiency of the bandwidth utilization.